| V1 |
|
100.00% |
| V2 |
|
94.38% |
| V2S |
|
100.00% |
| V3 |
|
47.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.920s | 0.000us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.620s | 0.000us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.690s | 0.000us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.510s | 0.000us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.880s | 0.000us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.780s | 0.000us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.690s | 0.000us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.880s | 0.000us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 10.080s | 0.000us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 5.330s | 0.000us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 800.450s | 0.000us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 800.450s | 0.000us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 7.030s | 0.000us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.890s | 0.000us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.680s | 0.000us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.500s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.500s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.620s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.690s | 0.000us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.880s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.860s | 0.000us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.620s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.690s | 0.000us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.880s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.860s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.640s | 0.000us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.360s | 0.000us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.360s | 0.000us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 1 | 10 | 10.00 | |||
| rv_timer_min | 2.940s | 0.000us | 1 | 10 | 10.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.230s | 0.000us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 18 | 20 | 90.00 | |||
| rv_timer_stress_all_with_rand_reset | 59.860s | 0.000us | 18 | 20 | 90.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 9664086050153875773919318284709931789226044825227763360467703469195429434516 | 75 |
UVM_FATAL @ 59711890 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd410a504) == 0x1
UVM_INFO @ 59711890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 95689659973979675266872841880863768350131990338625377808394301275811836170468 | 75 |
UVM_FATAL @ 237170818 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x86d4d704) == 0x1
UVM_INFO @ 237170818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 86163986034072179850381994100027090398776921621158104830689384060866553699020 | 75 |
UVM_FATAL @ 515849259 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe2e41904) == 0x1
UVM_INFO @ 515849259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 57653537989508356246296147366130075123743630663013836468455802450733441375782 | 75 |
UVM_FATAL @ 537042877 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb2f56104) == 0x1
UVM_INFO @ 537042877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 105510233702343372613692302805157234649129914731568499044512420430598532811106 | 75 |
UVM_FATAL @ 285446647 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe3a91904) == 0x1
UVM_INFO @ 285446647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 38248313278232320767219215201211546251696755171202764934619685550777609643294 | 76 |
UVM_FATAL @ 225107252 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe3f01904) == 0x1
UVM_INFO @ 225107252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 30335149887542847519240507279292633116254794587207730236642974684911209458401 | 75 |
UVM_FATAL @ 111855966 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x135be904) == 0x1
UVM_INFO @ 111855966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 39050148369452383868513150482979009295569659400495518042726163442032997069209 | 75 |
UVM_FATAL @ 238871983 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x379aef04) == 0x1
UVM_INFO @ 238871983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80091643496282685571979185595914356112708807661519884623159304542223990874188 | 76 |
UVM_FATAL @ 5208521551 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd44e304) == 0x1
UVM_INFO @ 5208521551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 92511891599076434608002856924436109963147328457780037414690623742450620775953 | 76 |
UVM_FATAL @ 108552515 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdb3e1b04) == 0x1
UVM_INFO @ 108552515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80309961859037608325760786285055149671148361039380534182147137683452808248081 | 77 |
UVM_FATAL @ 854857380 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x43141904) == 0x1
UVM_INFO @ 854857380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 103116891036183254478582432731752624614128447632342377896400381381311891906142 | 76 |
UVM_FATAL @ 1918877434 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6c35f904) == 0x1
UVM_INFO @ 1918877434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 113659589812592725937010337736888297150882426877207810853237747094045228781929 | 76 |
UVM_FATAL @ 81720418 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9c5c7f04) == 0x1
UVM_INFO @ 81720418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 107178387483785194963635710955077547019139862627679742044114625252511594376651 | 75 |
UVM_FATAL @ 122638569 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd6d2304) == 0x1
UVM_INFO @ 122638569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 51912905216962670151924644130470065748275050446788784340349744779659188255347 | 76 |
UVM_FATAL @ 876183467 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x30685d04) == 0x1
UVM_INFO @ 876183467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 94711348869328134411298329912410651196824523517435376976840242917447833876155 | 75 |
UVM_FATAL @ 224040955 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x49b6e704) == 0x1
UVM_INFO @ 224040955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 54503241162019641344803780338089323101509383070455606483365467006245491896733 | 77 |
UVM_FATAL @ 105150486 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x703dd504) == 0x1
UVM_INFO @ 105150486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 13321992813589132773014787948897635737126777316208737850366610202964952460599 | 76 |
UVM_FATAL @ 165354522 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xbb242704) == 0x1
UVM_INFO @ 165354522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 77419332533952845443541330626348533850882951604687632299744033467870288708287 | 75 |
UVM_FATAL @ 942507372 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb870ab04) == 0x1
UVM_INFO @ 942507372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28774815735639530636183299665427885206564130629624811271943478687586607149834 | 77 |
UVM_FATAL @ 1581843505 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9cdbdb04) == 0x1
UVM_INFO @ 1581843505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 68663002052524619708691478274131642602659056888714367813656566071492968622864 | 75 |
UVM_FATAL @ 107821012 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x93672f04) == 0x1
UVM_INFO @ 107821012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 83069511253433336044945621826253070775816067481695337958836076549561346989555 | 75 |
UVM_FATAL @ 244901933 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb6a22304) == 0x1
UVM_INFO @ 244901933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 59574576556975325432822320149284707476407071960332409410194867072755836927831 | 75 |
UVM_FATAL @ 377183338 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4743b704) == 0x1
UVM_INFO @ 377183338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 84357052657056495800492140906882064300322270969907775495354815603186666774001 | 75 |
UVM_FATAL @ 638967217 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x55ce1904) == 0x1
UVM_INFO @ 638967217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 96069203559427822703749227522608395590549567117416411889632876758221456824164 | 75 |
UVM_FATAL @ 604234896 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb6a97304) == 0x1
UVM_INFO @ 604234896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 48728152952059277499411181340557147383932866222032977327697704135339427017556 | 75 |
UVM_FATAL @ 636540534 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x55cc3904) == 0x1
UVM_INFO @ 636540534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 38486709501075667479687123788703472480829403958904692627618035957943841461610 | 75 |
UVM_FATAL @ 160724556 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7295f104) == 0x1
UVM_INFO @ 160724556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 93446256188323552520854152322049931193422412880808374113917983034718176090000 | 75 |
UVM_ERROR @ 177981544 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 177981544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 44251594882392555697795486557791584139341075512450487663154146040946216294919 | 75 |
UVM_ERROR @ 82774795 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 82774795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 5862421661387144522895106506297766537303510571038469186973659372745855124528 | 75 |
UVM_ERROR @ 186361333 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 186361333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 31608668918057460045117671679528396779426847692278805542723734488515925340571 | 75 |
UVM_ERROR @ 283959187 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 283959187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 9697454209997164952772751511272215553661901096677480144684226251202319490568 | 75 |
UVM_ERROR @ 86457809 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 86457809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 78481899278213322497393165508961175036466024096481114628813161182530797831406 | 75 |
UVM_ERROR @ 45220374 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45220374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 104388394837811772548314970615765303389016853342179930988152442694769491779235 | 75 |
UVM_ERROR @ 42246338 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 42246338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 43176101681285139364599396546540877422063268141917809323122428148124860672939 | 75 |
UVM_ERROR @ 86436481 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 86436481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 82111791773855486816027233663982684426577565761439968130831457988472423909224 | 75 |
UVM_ERROR @ 45060934 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45060934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 107007821333601896650888764237713219322277510181277988679093373809767965634830 | 75 |
UVM_ERROR @ 175873933 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 175873933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 102906652954290859059672909046417691120985414057258271466540161614517513230370 | 106 |
UVM_FATAL @ 4254451101 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 4254451101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 24193737692173899413722665687811103062514422293595380836926882326962673488325 | 214 |
UVM_ERROR @ 4604682408 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4604682408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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