Simulation Results: ac_range_check

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.84%
V2
96.27%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 45.000s 1408.119us 19 20 95.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 64.000s 8481.620us 18 20 90.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 15.000s 36.783us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 12.000s 40.405us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 59.000s 13720.516us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 45.000s 4497.059us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 13.000s 32.979us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 12.000s 40.405us 20 20 100.00
ac_range_check_csr_aliasing 45.000s 4497.059us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 5.000s 110.753us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 69.000s 2979.498us 1 1 100.00
stress_all 41 50 82.00
ac_range_check_stress_all 289.000s 12333.907us 41 50 82.00
alert_test 50 50 100.00
ac_range_check_alert_test 28.000s 39.331us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 6.000s 24.877us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 7.000s 711.501us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 7.000s 711.501us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 15.000s 36.783us 5 5 100.00
ac_range_check_csr_rw 12.000s 40.405us 20 20 100.00
ac_range_check_csr_aliasing 45.000s 4497.059us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 1021.283us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 15.000s 36.783us 5 5 100.00
ac_range_check_csr_rw 12.000s 40.405us 20 20 100.00
ac_range_check_csr_aliasing 45.000s 4497.059us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 1021.283us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 20.000s 1784.982us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 20.000s 1784.982us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 20.000s 1784.982us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 20.000s 1784.982us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 116.000s 21312.647us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 14.013us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 433.019us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 390.000s 2711.852us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 38.000s 2220.767us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke_racl 4422901803298428616056845836285029528113390140711604858284161383386472641592 4530
UVM_INFO @ 2069477384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 61274261748549570019241479121929665180445654414607650978653897087817063564333 4092
UVM_INFO @ 776902982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 114795041506222698431257261534826630902722224348641540898408069117383004949717 4757
UVM_INFO @ 1646354671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 60559725269927608981289742297821965986497219549299137485547544975673637510878 4520
UVM_INFO @ 465914147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 39762148704960687373241448088084823298298977720783176206898670211308466677732 22949
UVM_INFO @ 9035207016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 45425366555412544767872938509531015463440841667595531434763602671697231526778 9140
UVM_INFO @ 14090607698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 95785124861643078725207628424682197031049899290958797393628908851181737541146 4591
UVM_INFO @ 1107744983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 23848321380402213201482794424917037344817928002896690797863411173321417868818 9330
UVM_INFO @ 2039187255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 76920917620782159773500887865509105577846341791144576527087985533986787579670 9360
UVM_INFO @ 4460796479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 69559875213497014794259996887179674034230350381457079801593861089076951552990 18872
UVM_INFO @ 35733919327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 3729208963335851748274089493371547671189278426870848572048182040644333535945 8880
UVM_INFO @ 3833480062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
ac_range_check_stress_all 104885341676656687752096111545406328934433361209649500561738232925062191457544 13021
UVM_INFO @ 100547793318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---