Simulation Results: aes/masked

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.51 %
  • code
  • 98.10 %
  • assert
  • 98.57 %
  • func
  • 95.87 %
  • block
  • 98.19 %
  • line
  • 99.40 %
  • branch
  • 94.96 %
  • toggle
  • 98.05 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 74.567us 1 1 100.00
smoke 50 50 100.00
aes_smoke 30.000s 1101.634us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 67.311us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 71.078us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 6.000s 188.076us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 314.697us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 196.463us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 71.078us 20 20 100.00
aes_csr_aliasing 3.000s 314.697us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 30.000s 1101.634us 50 50 100.00
aes_config_error 24.000s 3197.157us 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
key_length 150 150 100.00
aes_smoke 30.000s 1101.634us 50 50 100.00
aes_config_error 24.000s 3197.157us 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
back2back 100 100 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
aes_b2b 35.000s 689.987us 50 50 100.00
backpressure 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 30.000s 1101.634us 50 50 100.00
aes_config_error 24.000s 3197.157us 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
aes_alert_reset 11.000s 502.751us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 4.000s 198.564us 50 50 100.00
aes_config_error 24.000s 3197.157us 50 50 100.00
aes_alert_reset 11.000s 502.751us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 27.000s 990.570us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 1551.023us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 27.000s 1575.515us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 11.000s 502.751us 50 50 100.00
stress 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
sideload 100 100 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
aes_sideload 13.000s 252.754us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 9.000s 1797.354us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 131.000s 12614.488us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 12.000s 531.779us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 5.000s 84.879us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 725.323us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 725.323us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 67.311us 5 5 100.00
aes_csr_rw 3.000s 71.078us 20 20 100.00
aes_csr_aliasing 3.000s 314.697us 5 5 100.00
aes_same_csr_outstanding 3.000s 105.447us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 67.311us 5 5 100.00
aes_csr_rw 3.000s 71.078us 20 20 100.00
aes_csr_aliasing 3.000s 314.697us 5 5 100.00
aes_same_csr_outstanding 3.000s 105.447us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 25.000s 817.366us 50 50 100.00
fault_inject 663 700 94.71
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 201.955us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 9.000s 2592.246us 5 5 100.00
aes_tl_intg_err 4.000s 501.185us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 501.185us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 11.000s 502.751us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
sec_cm_main_config_sparse 219 220 99.55
aes_smoke 30.000s 1101.634us 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
aes_alert_reset 11.000s 502.751us 50 50 100.00
aes_core_fi 12.000s 10029.410us 69 70 98.57
sec_cm_gcm_config_sparse 269 270 99.63
aes_gcm_save_restore 12.000s 531.779us 100 100 100.00
aes_config_error 24.000s 3197.157us 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
aes_core_fi 12.000s 10029.410us 69 70 98.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 223.502us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 89.668us 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
aes_sideload 13.000s 252.754us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 89.668us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 89.668us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 89.668us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 89.668us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 89.668us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 28.000s 2603.369us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 38.000s 2001.433us 49 50 98.00
sec_cm_main_fsm_redun 713 750 95.07
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
aes_ctr_fi 34.000s 188.254us 50 50 100.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 38.000s 2001.433us 49 50 98.00
sec_cm_cipher_fsm_redun 663 700 94.71
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
sec_cm_cipher_ctr_redun 329 350 94.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 38.000s 2001.433us 49 50 98.00
sec_cm_ctr_fsm_redun 384 400 96.00
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_ctr_fi 34.000s 188.254us 50 50 100.00
sec_cm_ghash_fsm_sparse 49 50 98.00
aes_fi 38.000s 2001.433us 49 50 98.00
sec_cm_ctrl_sparse 713 750 95.07
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
aes_ctr_fi 34.000s 188.254us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 11.000s 502.751us 50 50 100.00
sec_cm_main_fsm_local_esc 713 750 95.07
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
aes_ctr_fi 34.000s 188.254us 50 50 100.00
sec_cm_cipher_fsm_local_esc 713 750 95.07
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
aes_ctr_fi 34.000s 188.254us 50 50 100.00
sec_cm_ctr_fsm_local_esc 384 400 96.00
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_ctr_fi 34.000s 188.254us 50 50 100.00
sec_cm_ghash_fsm_local_esc 139 140 99.29
aes_fi 38.000s 2001.433us 49 50 98.00
aes_ghash_fi 9.000s 544.752us 90 90 100.00
sec_cm_data_reg_local_esc 663 700 94.71
aes_fi 38.000s 2001.433us 49 50 98.00
aes_control_fi 50.000s 10006.969us 285 300 95.00
aes_cipher_fi 39.000s 10143.587us 329 350 94.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 41.000s 2293.662us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 62182084261965551640578921581138857622587283344203165162987357748092431402680 355
UVM_INFO @ 251856544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 114671552622218862238004072688119871449429998703506113244390403755528455358464 398
UVM_INFO @ 1143840571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 33340272090354071065141956101493740690069654554906698631390178390766285319943 375
UVM_INFO @ 1114289318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 68200845332081093783605665194855386373650745845427825591362182202868815616828 269
UVM_INFO @ 320133870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 100485215137433156772851856999061377385915337976224387543284560052778668100462 246
UVM_INFO @ 269977188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 94869022830876265455696765051960268589115155028952799312652944082816860860962 194
UVM_INFO @ 125688362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 11168471168149597100354406379476318209251776697738670230487565040787445157495 1085
UVM_INFO @ 2293662325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 45854053190177525972172366320055157270009745191712042180248770273460022507770 295
UVM_INFO @ 1057573529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
aes_control_fi 5583835204309946193786884215416393402632279959919223731677191517109440002961 None
aes_control_fi 21126008964952364410952741450444654438627156293309149019724826123941256300615 None
aes_cipher_fi 36715829993033569810035006492850198277098364001339722424032615857668413197628 None
aes_control_fi 107477952655552614303651121584415490867032894045351982318570619464797372250886 None
aes_control_fi 20853493208700590215979653729048801948781855873378522338883748709688260986804 None
aes_cipher_fi 114461664331902197232155077841087970280821525379597512766567120102195248259717 None
aes_control_fi 110668563601682874624831688716539388993728242107833979985495615726944773593503 None
aes_control_fi 92126394369951848528786548070111745640759300747260336059661986339201329378017 None
aes_control_fi 39246120358547578793817317033728757591715447789498253335922138551905656900867 None
aes_control_fi 107979286589381010540782713466099174775995538173670601710409600357664883835382 None
aes_control_fi 21535956077880946355204855847639087903067874323801475161587622621139644880193 None
aes_cipher_fi 53826197293019195712399593426953248834092604345692687956159456127814921625770 None
aes_cipher_fi 63381407564389749471084507924108180283051121140949900633862155822990750665397 None
aes_cipher_fi 94919471758041630709109997252048276151727886548007757333025998857551504031157 None
aes_control_fi 75855962525162459391735341644973790659247138096593618478763887825625443073947 None
aes_control_fi 97325676343719784856363038548691015572598096949297568908200432917689790517108 None
aes_control_fi 4035789697565335827813538112331698855156552387822528970371202783675711340548 None
aes_cipher_fi 88737350599039140461098641672153593598302723917062253766604337676752246529318 None
aes_cipher_fi 114006916240621245109313602317332283787577002738916225809330911089570664694287 None
aes_cipher_fi 48817394407342848815259357928844101174832813012094208982811538426600582224890 None
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 78993947278187432404056527444517053600379829408137828931777604260973686508619 160
UVM_INFO @ 78954724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed
aes_stress_all_with_rand_reset 109775964745181124107402326300025141841540578076369726624802514036878703585153 155
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 197314902 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 197314902 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 197314902 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 197314902 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 49170059780311380845152025338099946489772980633763933482783480483746396731615 145
UVM_INFO @ 10143586820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91201488309621764636019519369752086818453016802626026638587266291133272517086 149
UVM_INFO @ 10013938176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57287420279974195393855449292426072529917814159594351688687564185755036828096 144
UVM_INFO @ 10010468257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 86019612353316569953306394940769020707031119262396374575641808197252039796203 147
UVM_INFO @ 10083869823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 44842892991658932165097979634978257921115315507321781448318915124107142837999 156
UVM_INFO @ 10021823104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 84560867957753072433797282727276747373102178463836963616166903390012879134699 146
UVM_INFO @ 10015815434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 82702141828978702901904134639987177101613110070872770276297578009511794363261 140
UVM_INFO @ 10074211272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 6557310588196106588471130144536351080983899797522316729251552727206530096935 151
UVM_INFO @ 10006761304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 50541256768249218556950718147314468828811175915322666219972509247405618125728 154
UVM_INFO @ 10016235331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 16037289907326431151116674001372456127713961811005042789335395399999142944128 141
UVM_INFO @ 10028775542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 70824824419410377743840172935810372550765485846831220946640566267819350607317 143
UVM_INFO @ 10020820330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 41152609414928290910183808003789550894554216037429444677942841456187348863367 142
UVM_INFO @ 10017363210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 59809006960585694138750765654953302298803271759036957259337021289335809537802 142
UVM_INFO @ 10012589350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
aes_fi 18774937230883421368049899216095266638365284659794184465951266120413977408706 2207
($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
|
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1142): (time 29492078 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 29444459 PS)
UVM_ERROR @ 29492078 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 5299177500995355579189952371173990715879432870575911513630937076233780512289 145
UVM_INFO @ 10029409542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 14677381032722386515738766497158474103876910720341547544572466054190798232723 142
UVM_INFO @ 10036764272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 7891545100479237910844068365195433128298232354895812246181852072975006848519 151
UVM_INFO @ 10005459806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 63310153111354750033018331578949015724351764296378896758940291543058744636367 153
UVM_INFO @ 10006968793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---