Simulation Results: alert_handler

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.04 %
  • code
  • 98.83 %
  • assert
  • 98.92 %
  • func
  • 99.36 %
  • line
  • 99.99 %
  • branch
  • 99.99 %
  • cond
  • 97.46 %
  • toggle
  • 96.72 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.63%
V2S
99.25%
V3
64.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
alert_handler_smoke 81.430s 1224.285us 50 50 100.00
csr_hw_reset 5 5 100.00
alert_handler_csr_hw_reset 9.780s 971.582us 5 5 100.00
csr_rw 20 20 100.00
alert_handler_csr_rw 12.710s 126.405us 20 20 100.00
csr_bit_bash 5 5 100.00
alert_handler_csr_bit_bash 416.260s 26898.364us 5 5 100.00
csr_aliasing 5 5 100.00
alert_handler_csr_aliasing 345.180s 6686.678us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
alert_handler_csr_mem_rw_with_rand_reset 16.740s 916.312us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
alert_handler_csr_rw 12.710s 126.405us 20 20 100.00
alert_handler_csr_aliasing 345.180s 6686.678us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 50 50 100.00
alert_handler_esc_alert_accum 425.840s 6575.944us 50 50 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 79.580s 1322.733us 50 50 100.00
entropy 50 50 100.00
alert_handler_entropy 3256.630s 64304.549us 50 50 100.00
sig_int_fail 50 50 100.00
alert_handler_sig_int_fail 78.920s 1068.636us 50 50 100.00
clk_skew 50 50 100.00
alert_handler_smoke 81.430s 1224.285us 50 50 100.00
random_alerts 50 50 100.00
alert_handler_random_alerts 76.750s 1412.868us 50 50 100.00
random_classes 50 50 100.00
alert_handler_random_classes 76.850s 5506.138us 50 50 100.00
ping_timeout 22 50 44.00
alert_handler_ping_timeout 533.770s 79248.482us 22 50 44.00
lpg 98 100 98.00
alert_handler_lpg 3201.420s 58862.199us 48 50 96.00
alert_handler_lpg_stub_clk 3509.400s 982302.501us 50 50 100.00
stress_all 49 50 98.00
alert_handler_stress_all 3907.980s 82801.348us 49 50 98.00
alert_handler_entropy_stress_test 20 20 100.00
alert_handler_entropy_stress 79.560s 2204.333us 20 20 100.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 5.160s 47.655us 20 20 100.00
intr_test 50 50 100.00
alert_handler_intr_test 2.770s 21.627us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
alert_handler_tl_errors 31.760s 1355.029us 20 20 100.00
tl_d_illegal_access 20 20 100.00
alert_handler_tl_errors 31.760s 1355.029us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
alert_handler_csr_hw_reset 9.780s 971.582us 5 5 100.00
alert_handler_csr_rw 12.710s 126.405us 20 20 100.00
alert_handler_csr_aliasing 345.180s 6686.678us 5 5 100.00
alert_handler_same_csr_outstanding 56.470s 2988.849us 20 20 100.00
tl_d_partial_access 50 50 100.00
alert_handler_csr_hw_reset 9.780s 971.582us 5 5 100.00
alert_handler_csr_rw 12.710s 126.405us 20 20 100.00
alert_handler_csr_aliasing 345.180s 6686.678us 5 5 100.00
alert_handler_same_csr_outstanding 56.470s 2988.849us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 414.000s 6104.483us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 414.000s 6104.483us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 414.000s 6104.483us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 414.000s 6104.483us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1338.180s 20861.776us 20 20 100.00
tl_intg_err 25 25 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
alert_handler_tl_intg_err 99.370s 1488.818us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
alert_handler_tl_intg_err 99.370s 1488.818us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 414.000s 6104.483us 20 20 100.00
sec_cm_ping_timer_config_regwen 50 50 100.00
alert_handler_smoke 81.430s 1224.285us 50 50 100.00
sec_cm_alert_config_regwen 50 50 100.00
alert_handler_smoke 81.430s 1224.285us 50 50 100.00
sec_cm_alert_loc_config_regwen 50 50 100.00
alert_handler_smoke 81.430s 1224.285us 50 50 100.00
sec_cm_class_config_regwen 50 50 100.00
alert_handler_smoke 81.430s 1224.285us 50 50 100.00
sec_cm_alert_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 78.920s 1068.636us 50 50 100.00
sec_cm_lpg_intersig_mubi 48 50 96.00
alert_handler_lpg 3201.420s 58862.199us 48 50 96.00
sec_cm_esc_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 78.920s 1068.636us 50 50 100.00
sec_cm_alert_rx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 3256.630s 64304.549us 50 50 100.00
sec_cm_esc_tx_intersig_bkgn_chk 50 50 100.00
alert_handler_entropy 3256.630s 64304.549us 50 50 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 89.320s 2020.277us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 32 50 64.00
alert_handler_stress_all_with_rand_reset 536.810s 17238.922us 32 50 64.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 36931682864552867672789446308399399389216928877890242296393996278052530314483 82
UVM_INFO @ 115737510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 30744009406466743356898821693523905833188719972353457817868014848988643800799 131
UVM_INFO @ 15245434696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 92942526652121642016261031183683368847093944980741294662102410660156795566372 93
UVM_INFO @ 3074736617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 111115953086400606642538591345280591150558052262802625496000092857185685390320 108
UVM_INFO @ 18589364906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 59321676069919064475200291532063462533876481545411633285832933212044770789005 188
UVM_INFO @ 3400675071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 1629382909028245138705732671572587045043946223787546683499366755706843444542 120
UVM_INFO @ 844367245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 81489554008370386987074699427499609540691745149725397827131291798539956213436 139
UVM_INFO @ 10164546815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 64295258550826359678401546391879469416187676214802261654528887362144030560265 122
UVM_INFO @ 6865517106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 104250746605026857460274440849870721758735202102407132304635796967197649044953 102
UVM_INFO @ 1852159357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 64674789108090232353822791291791772965319605976532169167945110925059087437630 120
UVM_INFO @ 2376237577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 102726398103405617642526067256709904026189816103317505340980453610666843164375 92
UVM_INFO @ 757753742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 109634806511102389213406732372996969441374003509833343979167588430321433420142 130
UVM_INFO @ 5085140924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 94340543005987642636175188161755334746044161629916881352031582331362301785525 84
UVM_INFO @ 503686514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 3113528798967185611119273602937784138748264344831423280754740368319494618459 188
UVM_INFO @ 19471795606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 96547048011491084005487455065695550315176255563905320901427644873194775914157 106
UVM_INFO @ 4577611976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 56621781506344947273558015287094510363315321487996069305931662996442744197169 93
UVM_INFO @ 2129320414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_stress_all_with_rand_reset 28679521532272450063714307211355721352438302772520577421172187923247003610789 154
UVM_INFO @ 12859635893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 86740389952618593364543412023083122116828602673285965335510960435776913464434 93
UVM_INFO @ 5910022395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 68194900352070044323218249295611117570891068356338178962366730861431673759694 94
UVM_INFO @ 6961211470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 42181350224088927845746833818887449268216386719553815103315703139336914971478 105
UVM_INFO @ 5158930533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 15491077719544526648352084975549763940177956977189459658233743695347093032240 114
UVM_INFO @ 4278263914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 78851410456744286654187974875418466547510496509764953628238833671017390711537 84
UVM_INFO @ 8685988747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 41614390943533710755436015291750834349972129376132007870904838363734107016506 87
UVM_INFO @ 2757754218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 79384230227586841636721334343466105009471275040185974347375605579377570180718 93
UVM_INFO @ 20073797874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 105529212694533608094982352944185466980640165678810759490625844818689780844825 93
UVM_INFO @ 13175220864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 111395315358254864242051795406384203458122201234789279129432666042496702768935 87
UVM_INFO @ 1320022396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 48802294820533160966622430213241178575511115026052386692246635514624419550982 114
UVM_INFO @ 4975258353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 78423462978018286768116483512822481671157285209889931732182912254362961017483 120
UVM_INFO @ 31380701751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 19391362830726696453176629688411862737804194128659879995370757322321473797492 114
UVM_INFO @ 5697719678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 36021203654369707915857952255108957262752454441077311244523851688148194557152 96
UVM_INFO @ 4685871430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 46930154496453100821642318535123390286425332336064124388979755771318371944116 93
UVM_INFO @ 2829975597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 34567686738863926986322842988292717890927436209012659597188218900267946823007 85
UVM_INFO @ 499366637101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 8680225827269233278629536017144793456275126153654549250992118432169357352499 114
UVM_INFO @ 22693283989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 30171626157855833736825537429556173202163063919781758962868768561957664410479 108
UVM_INFO @ 12978533860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 14454644001495864925010491861388743785734180622111958327436028334685465988229 87
UVM_INFO @ 8790682383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 111738478393493141809690536670557570658694080817324643367946401365115589415217 93
UVM_INFO @ 13445378429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 54926584939237687694165481488751579451094218468506182702290385686167979671294 87
UVM_INFO @ 1356339521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 18567696627055188388974920460580543593316480577651496789727045275694423211350 93
UVM_INFO @ 4828623770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 16402624005667002275711377839262100253557354772291824629555713951550501742125 123
UVM_INFO @ 29039118055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 32536778583479362065896486437214925879573948721977765109689882611675077370039 87
UVM_INFO @ 2439940425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_lpg 63939584496190605805464211579356438534836266078177737321173850364249443134732 80
UVM_INFO @ 53608507930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:598) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*])
alert_handler_ping_timeout 29605196650374963995295526374648239197703152307371266848732635548344092128807 80
UVM_INFO @ 1056738458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 81964325710071309620102219873658525056570759445065065079546290050394184904158 80
UVM_INFO @ 323295565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 67070569377531584394929857360533872710104535886055781656410880033913467575586 80
UVM_INFO @ 1228462395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 7921173129819832044295527514081298558412010933169355584163258158262312997495 80
UVM_INFO @ 790893698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 52800079323774587696638869491978940717944274122881525540355051186030487576578 80
UVM_INFO @ 2194941577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 31340449688941409761742894149384304670593572107509571798338218842522833265133 96
UVM_INFO @ 1620025989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail)
alert_handler_stress_all 42610465623670244740265376154127754919761454684250865246685820336550810788633 141
UVM_INFO @ 2216798232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:343) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*])
alert_handler_ping_timeout 101920533667176378144795662535302866972192349525143103493878198881797552731941 87
UVM_INFO @ 3993204986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---