Simulation Results: csrng

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.19 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 90.50 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
97.07%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 33.000s 26.835us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 33.000s 15.163us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 33.000s 49.406us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 54.000s 1282.620us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 33.000s 43.868us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 33.000s 80.561us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 33.000s 49.406us 20 20 100.00
csrng_csr_aliasing 33.000s 43.868us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
alerts 500 500 100.00
csrng_alert 60.000s 4612.490us 500 500 100.00
err 500 500 100.00
csrng_err 33.000s 18.898us 500 500 100.00
cmds 7 50 14.00
csrng_cmds 149.000s 2958.149us 7 50 14.00
life cycle 7 50 14.00
csrng_cmds 149.000s 2958.149us 7 50 14.00
stress_all 50 50 100.00
csrng_stress_all 1952.000s 155070.853us 50 50 100.00
intr_test 50 50 100.00
csrng_intr_test 33.000s 22.149us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 33.000s 23.893us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 35.000s 116.061us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 35.000s 116.061us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 33.000s 15.163us 5 5 100.00
csrng_csr_rw 33.000s 49.406us 20 20 100.00
csrng_csr_aliasing 33.000s 43.868us 5 5 100.00
csrng_same_csr_outstanding 34.000s 79.968us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 33.000s 15.163us 5 5 100.00
csrng_csr_rw 33.000s 49.406us 20 20 100.00
csrng_csr_aliasing 33.000s 43.868us 5 5 100.00
csrng_same_csr_outstanding 34.000s 79.968us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
csrng_tl_intg_err 34.000s 59.571us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 33.000s 39.770us 50 50 100.00
csrng_csr_rw 33.000s 49.406us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 60.000s 4612.490us 500 500 100.00
sec_cm_intersig_mubi 50 50 100.00
csrng_stress_all 1952.000s 155070.853us 50 50 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 60.000s 4612.490us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
sec_cm_constants_lc_gated 50 50 100.00
csrng_stress_all 1952.000s 155070.853us 50 50 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 60.000s 4612.490us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 34.000s 59.571us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
csrng_sec_cm 37.000s 194.956us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 39.000s 288.276us 200 200 100.00
csrng_err 33.000s 18.898us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 2.000s 10.197us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 102575093204088765905973189279724681330661091542118527372471162357004787522870 130
UVM_INFO @ 71000246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 106443939123947684776319537039551976163012631592489606083043260679586106449731 130
UVM_INFO @ 136015336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 107085914981219611729260744163106655916597228723329710425131376368759598970281 150
UVM_INFO @ 1841110485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 51410806615646200589219056331872692358889757683754155992119173990724535299420 130
UVM_INFO @ 463250449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 4552362481750372824973696353420001140772670480911788868209119707378832774347 130
UVM_INFO @ 75143936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 97201406582431327676337501814887896789853755904132511241684492336166843038381 130
UVM_INFO @ 148314498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 64000278632604874565180143792541301118298066070541218810210855818872430016278 140
UVM_INFO @ 1349256396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23912020895876264103031519683026400610738204831229912256741992872081621366720 130
UVM_INFO @ 64448061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52490278027612347586826019264415255152630976587274664926508891460830750396563 130
UVM_INFO @ 333814800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 35899760862204207767224563253765245599836647470345809984060135908486020142471 130
UVM_INFO @ 16661558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 45756596995458618848832287970981344820927904973034403347369197986575580459007 130
UVM_INFO @ 226409126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52060129877334147841328136336653342447680450817141567765284128337175572777060 130
UVM_INFO @ 79650541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31973566575255148272320420136421082156102689330686279080149348719659656070368 130
UVM_INFO @ 17458732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 102784487477040304525270213392274931733695300254404027656763647032472096866191 130
UVM_INFO @ 40363403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 38911905253640814801339562733114163147518748953915834815742102812760340722473 130
UVM_INFO @ 52279156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 35645068351283347628727462153853065274570356189037323185564150060321799347956 130
UVM_INFO @ 60259007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 87328918221890248825945988519528505489757955746721147694071116154202387645079 130
UVM_INFO @ 60938044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 12536753476143547335189658550746586367615962919742574336317013826562089155771 130
UVM_INFO @ 188188221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 76110110829027964962875688066539789176653996328151373411121883415900300321690 130
UVM_INFO @ 41797156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 106491596328646107533956659278588951837447191673734540429608554309872900250444 130
UVM_INFO @ 156027322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23483384624030473474983502273063553147090740109687786702282825954871808387699 130
UVM_INFO @ 632505552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 10312055542830231101217522278596009354041332424038013920945142302908617083872 130
UVM_INFO @ 171237851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 39754426869618037992564988801464170411783557341831934302606801593375296749139 130
UVM_INFO @ 33495561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108315479028925063943521427517068312782142959105664058830410439323217183021196 130
UVM_INFO @ 143233309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 112346478634361882358553764377789995872521756472851177436366772494844272199206 130
UVM_INFO @ 33679764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 81636241718449192660265084117383791325027675101738923539516262323137903088283 130
UVM_INFO @ 60706824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 60560514173997106675035145863816255654906942638694667750735184134837531050972 130
UVM_INFO @ 1244566602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 26826728367660460870321128828810587652412165545367074685655979292718400336081 130
UVM_INFO @ 157796229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 45673983736812972426670793984382725294198527781545687424323787329628454910843 130
UVM_INFO @ 65945220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31765706156756888838576537431880099594304470336212998387822994827130445641150 130
UVM_INFO @ 11047834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 22109315739022695714918908980234513456906366919209428294864126721540239058824 130
UVM_INFO @ 111752788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 2096550042236661649634626506835140822486201105147881525168672962252099007674 130
UVM_INFO @ 6488756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 86975275915707909849955576565132187492018737447324615042613365515389993846732 130
UVM_INFO @ 177400415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103832024160172667939367872775731708768570685396187589302201747107001595647828 130
UVM_INFO @ 60455562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 22811528764010374360044714635120836607291714665388118411545682185993641606053 130
UVM_INFO @ 205841754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66668763397453537484675102213293541562080913530690926184113024077642139498292 130
UVM_INFO @ 1117483788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 42427581644013090477619706902894652106323558102187485315082408014859760734179 140
UVM_INFO @ 202498260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 96495108712119337173332250156378036919070932488080927919207314425718298115141 None
csrng_stress_all_with_rand_reset 79763519394823281565431083553310129535731916105423253919800966647370398731915 None
csrng_stress_all_with_rand_reset 47250859307767504797260670090097267062316521917437619900062121222077520061197 None
csrng_stress_all_with_rand_reset 53269770527709270892744779264708196097875722081559379968448319340441573710 None
csrng_stress_all_with_rand_reset 42330393369608941007629270614608165858777922205315254092760054880485611000801 None
csrng_stress_all_with_rand_reset 40852489417912331169269801980350048408884963781461660971548524348911520302361 None
csrng_stress_all_with_rand_reset 104513300946452382125050420356066477238339120553395043041455345410061272864524 None
csrng_stress_all_with_rand_reset 15477591963160579732432209412312222442594065174597699869447350880097437982603 None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started
csrng_stress_all_with_rand_reset 9126329141123130648263696599345737460533713301548874508022016407440600861068 111
UVM_INFO @ 2678503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 109428632712377308315726355981054361345972785789037738312972866897797057356283 111
UVM_INFO @ 10197464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits
csrng_cmds 69535719169930867006290961081388868628324890349010477918003967705226271621970 133
UVM_INFO @ 39528317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 72601628491256118179101697914658097639546177553377285781420601884904665933969 133
UVM_INFO @ 1045528645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 26252604948062334828544581472229236430392155134364883297469586194366590812928 133
UVM_INFO @ 35404710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly
csrng_cmds 47937837859156032849809201429350488308217201957361681821955043455970579479788 138
UVM_INFO @ 112221805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 72202082882693011599219525728810882656245338494093107247679574648011936069783 148
UVM_INFO @ 52310465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 50096236279229916394018459831392839162468160339911441277150807132041194440359 138
UVM_INFO @ 17099007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---