Simulation Results: edn/edn0

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 96.05 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 93.55 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
92.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.350s 27.765us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.230s 90.388us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.380s 18.769us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.920s 500.449us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 2.140s 698.745us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.820s 35.848us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.380s 18.769us 20 20 100.00
edn_csr_aliasing 2.140s 698.745us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 120.050s 21970.552us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 120.050s 21970.552us 300 300 100.00
genbits 300 300 100.00
edn_genbits 120.050s 21970.552us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.550s 20.742us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.740s 30.176us 200 200 100.00
errs 100 100 100.00
edn_err 1.680s 20.325us 100 100 100.00
disable 92 100 92.00
edn_disable 2.930s 500.000us 49 50 98.00
edn_disable_auto_req_mode 7.460s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 8.250s 388.238us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.240s 27.130us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.580s 50.752us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 4.540s 116.177us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 4.540s 116.177us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.230s 90.388us 5 5 100.00
edn_csr_rw 1.380s 18.769us 20 20 100.00
edn_csr_aliasing 2.140s 698.745us 5 5 100.00
edn_same_csr_outstanding 1.970s 161.441us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.230s 90.388us 5 5 100.00
edn_csr_rw 1.380s 18.769us 20 20 100.00
edn_csr_aliasing 2.140s 698.745us 5 5 100.00
edn_same_csr_outstanding 1.970s 161.441us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 8.490s 1175.217us 5 5 100.00
edn_tl_intg_err 5.110s 283.365us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.380s 16.513us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.740s 30.176us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.490s 1175.217us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.490s 1175.217us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.490s 1175.217us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.490s 1175.217us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.740s 30.176us 200 200 100.00
edn_sec_cm 8.490s 1175.217us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.740s 30.176us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 5.110s 283.365us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 46 50 92.00
edn_stress_all_with_rand_reset 183.390s 102620.191us 46 50 92.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 90559152601658885806871812182622107754186457059605224888244414654698067276822 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 36376006795888882224301120655004581135576404270506738315771894322234932313525 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 89152708421566079334436142246530731203964625700329220656341976803229416352066 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 85034639029949805944268354675642044790395276628075511744358506044407516237475 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable 42722635171552568906615547303368691017195915017982458146902787344868420712285 85
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 17477032035042333450732867051358438854823236673360634734787982627695781611252 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 4714575220162906700722944803939781059753105376744839447698206550874792648336 188
UVM_INFO @ 2166683959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 10981477096952702752795684299805439548654000632819210499241790807925042387574 153
UVM_INFO @ 1651310004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 85117474331479554927920486530075323032882474376961710311345718904761400243574 182
UVM_INFO @ 1003282913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37811483495501307305773758787824581459653676475627544851575140207252034159203 195
UVM_INFO @ 2294236524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 69333090011995103074382259072212399239679519916663368315383297620364956276846 88
UVM_INFO @ 17730764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2250620451058913532168796430426563623093137199175012328126070057797926567755 88
UVM_INFO @ 61346725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---