Simulation Results: edn/edn1

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.26 %
  • code
  • 96.41 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
99.38%
V2S
100.00%
V3
82.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.040s 40.632us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.080s 97.891us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.980s 39.818us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.850s 675.755us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.170s 66.445us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.630s 25.889us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.980s 39.818us 20 20 100.00
edn_csr_aliasing 1.170s 66.445us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 104.510s 9102.545us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 104.510s 9102.545us 300 300 100.00
genbits 300 300 100.00
edn_genbits 104.510s 9102.545us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.070s 40.917us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.310s 106.954us 200 200 100.00
errs 100 100 100.00
edn_err 1.200s 28.573us 100 100 100.00
disable 94 100 94.00
edn_disable 0.950s 14.248us 50 50 100.00
edn_disable_auto_req_mode 14.390s 500.000us 44 50 88.00
stress_all 50 50 100.00
edn_stress_all 7.400s 429.357us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.020s 14.497us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.420s 94.565us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.190s 965.447us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.190s 965.447us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.080s 97.891us 5 5 100.00
edn_csr_rw 0.980s 39.818us 20 20 100.00
edn_csr_aliasing 1.170s 66.445us 5 5 100.00
edn_same_csr_outstanding 1.210s 39.065us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.080s 97.891us 5 5 100.00
edn_csr_rw 0.980s 39.818us 20 20 100.00
edn_csr_aliasing 1.170s 66.445us 5 5 100.00
edn_same_csr_outstanding 1.210s 39.065us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 4.360s 405.105us 5 5 100.00
edn_tl_intg_err 2.470s 187.010us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.000s 18.506us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.310s 106.954us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.360s 405.105us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.360s 405.105us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.360s 405.105us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.360s 405.105us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.310s 106.954us 200 200 100.00
edn_sec_cm 4.360s 405.105us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.310s 106.954us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.470s 187.010us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 41 50 82.00
edn_stress_all_with_rand_reset 128.410s 22788.702us 41 50 82.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 66499358181117403951459452826386461736082851916690425342713542297513790193708 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 61067048880497215346510743489068145603405694822686606521818523814131700222996 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11674734142838562418319923180761812632660475241098537180069153437529110558811 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 75571143000225509022423941263172853674032155166734280954414729039672665614221 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62242241951093073617762861742313322299516026396231595193882901689249265846442 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 31191229986946984810924372495600935591800983675049233561684127560644310463975 182
UVM_INFO @ 591485840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 79804167282131018776918614888986042995516863654532799412606397878883664717189 171
UVM_INFO @ 2116750187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 14130380950121271731958667452496226717990382124667692888774630534671896009771 152
UVM_INFO @ 389766955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 15010016955380234904208515765224175476758403463517050925825634890626278325776 246
UVM_INFO @ 2062812413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 77618113012930690937750902639796128448005445908424386490292874201928649810312 320
UVM_INFO @ 2077388157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 7441540209844193542424082746636335850820986539447562239259528778123851470583 269
UVM_INFO @ 2451529823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 93014757178343900328699352784200281606042796600249576130201661481392076977213 176
UVM_INFO @ 1054194444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 106514997078305862620771502418846935952207689495267390114244690474833657670010 146
UVM_INFO @ 967999975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 10067576382732259152927369517901402033559552156978910886925559373962794164928 352
UVM_INFO @ 3711310207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 74177791776112200257069880744814081402899730631566449919288981529066965479823 88
UVM_INFO @ 28281324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---