Simulation Results: gpio

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.47 %
  • code
  • 92.56 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.89 %
  • branch
  • 98.38 %
  • cond
  • 95.32 %
  • toggle
  • 94.19 %
  • FSM
  • 75.00 %
Validation stages
V1
100.00%
V2
92.54%
V2S
92.00%
V3
43.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 1.830s 209.348us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.870s 723.356us 50 50 100.00
gpio_smoke_en_cdc_prim 2.440s 107.322us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 2.060s 243.849us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 1.120s 60.185us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 1.140s 475.882us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 7.680s 11282.203us 5 5 100.00
csr_aliasing 5 5 100.00
gpio_csr_aliasing 3.100s 179.239us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.440s 38.923us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
gpio_csr_rw 1.140s 475.882us 20 20 100.00
gpio_csr_aliasing 3.100s 179.239us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.750s 223.470us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.660s 30.219us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.480s 206.624us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 1.950s 293.964us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 4.260s 561.341us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 3.450s 77.326us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 21.060s 9780.772us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 6.300s 1674.515us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.580s 171.708us 50 50 100.00
stress_all 3 50 6.00
gpio_stress_all 100.170s 8082.576us 3 50 6.00
alert_test 50 50 100.00
gpio_alert_test 0.930s 17.877us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.930s 47.670us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 3.690s 297.162us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 3.690s 297.162us 20 20 100.00
tl_d_outstanding_access 47 50 94.00
gpio_csr_rw 1.140s 475.882us 20 20 100.00
gpio_same_csr_outstanding 1.860s 341.369us 17 20 85.00
gpio_csr_aliasing 3.100s 179.239us 5 5 100.00
gpio_csr_hw_reset 1.120s 60.185us 5 5 100.00
tl_d_partial_access 47 50 94.00
gpio_csr_rw 1.140s 475.882us 20 20 100.00
gpio_same_csr_outstanding 1.860s 341.369us 17 20 85.00
gpio_csr_aliasing 3.100s 179.239us 5 5 100.00
gpio_csr_hw_reset 1.120s 60.185us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 23 25 92.00
gpio_tl_intg_err 3.520s 890.939us 18 20 90.00
gpio_sec_cm 1.450s 477.586us 5 5 100.00
sec_cm_bus_integrity 18 20 90.00
gpio_tl_intg_err 3.520s 890.939us 18 20 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 43 50 86.00
gpio_rand_straps 0.910s 13.516us 43 50 86.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 17.650s 1491.522us 0 50 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
gpio_inp_prd_cnt 0.930s 12.404us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -*
gpio_stress_all_with_rand_reset 67474334165124347832420209163354553083943791808324051654935342652922233047757 80
UVM_INFO @ 141748064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 95826972681970023887329003262200333937069718711259481275939725321331481038233 78
UVM_INFO @ 110394925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 21645236015008747800724862972019082293415802338502164193643557242247681630944 78
UVM_INFO @ 2959144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 35508086325276653741208080470274960328179587003707679076013541908239173685546 78
UVM_INFO @ 23007582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 108052606380386638526170063137152671865831517933447099219455980461696903071982 81
UVM_INFO @ 497510512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 83390532949675413962238194897023481232739997687331118178235540614874260809400 307
UVM_INFO @ 2071961996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 40369991860913862895512357262318682819454903743341750237465991729243150043197 78
UVM_INFO @ 118607034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 94628533829645746766241693985225385143157897796839687342930571054178652959478 78
UVM_INFO @ 6926059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 55034767732456246022671269791178566722229038578934650229062481035736832877993 78
UVM_INFO @ 119652328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17171193832412414022960749843848581567897404214938509339534638581852435100495 78
UVM_INFO @ 3129547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 92835215411648577031113610226573215536951462809954121914430852617808755401976 78
UVM_INFO @ 106570146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 104086538796923689149925056758230489117042167356349473265600934232056592658118 119
UVM_INFO @ 1663530196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 28378487082728834712678181288102977700567913815938583562874303762889571240726 78
UVM_INFO @ 1948058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 46402279586044072651064040051694873961819031944252616721814407438286911352261 81
UVM_INFO @ 800539991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 26268820239146055900525221075704792614295439555538795729204847543052178690402 78
UVM_INFO @ 81301567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52691093018305443934818681080634967764944330330223821103649716454074275194207 78
UVM_INFO @ 2017387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 35397829356304353602029573529053378710650262374398269717251757221312166864864 159
UVM_INFO @ 232141480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 50471124410487036895570022161782049210034821302352002642922679539977419814381 78
UVM_INFO @ 11757201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 90788266825457460548625073266998013926790531554814110911095979466333267609246 79
UVM_INFO @ 204339783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 63518450354318726240295594659074350870088326025792092875388080705552797719111 126
UVM_INFO @ 1429420222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 38337515910506587780791915337554758015568546355902883476100630955139663591665 78
UVM_INFO @ 1326031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52411326734205129811901717090755482561854044812602963023757800241590513959645 79
UVM_INFO @ 739885925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57792635586878230453792182780355594500751395615074971230322792631875272890677 498
UVM_INFO @ 3969273912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52325502982566426708194081738064835007636904260016990293863984584537266630279 78
UVM_INFO @ 41522865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
gpio_stress_all 30912148160209170162016877471443496518940479786042279956058049287203386819192 158
UVM_INFO @ 3784111306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114607738608833698780832665721407921778761441458910407922834332835881986982440 351
UVM_INFO @ 2376836583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1611970903459566123276115363057427942634809374920311855292201210235104611453 315
UVM_INFO @ 2965615361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84971174732796490849832224692218313592998175275684947824865340081462840641212 1166
UVM_INFO @ 33309167597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1716693106158814456333775839423548892420080008273894533033728120085953883519 1211
UVM_INFO @ 3771246990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114536651468368323456123582294280907435088724896486042109394631519077035900360 219
UVM_INFO @ 1142908759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13540430645406373405871033649510450088010736541021914463940341789342321509528 1245
UVM_INFO @ 4136215164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 115148416399445069708785161892788220876914367945622655679321652624105579338014 75
UVM_INFO @ 1532322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10834363709803393039597270989815816971946231794306614595751615363441583517852 389
UVM_INFO @ 2206956703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79045001368354468195444957070906510988687804898010214772603449039096331661411 1364
UVM_INFO @ 4407136411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 73844922597709036191996740276595214816248439516042372259636896922103571628992 313
UVM_INFO @ 972226842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 94679199514098532501975682580782196604315181268822241944084466652387115093218 277
UVM_INFO @ 6427978000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 85808499377609942483625162062549970187936052958685245099165836730489599739221 77
UVM_INFO @ 168965579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 51662628839898363343255260360665093321100214790819206499354587987173906933260 2237
UVM_INFO @ 20777054414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 70949434355583945439444909155814413962823323339500949076481051999402201074363 1152
UVM_INFO @ 6974380580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 51303147277278209906956540195435962266341565986986861749493124908195431572709 143
UVM_INFO @ 361030150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 32318396192754329012750155516925430344801527189358248985985422669571261476754 1191
UVM_INFO @ 9313922883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 6767534584873086206576539995751625786032344281976244018075410111705650477039 1637
UVM_INFO @ 2323089078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 59053220361006814496197604993914563121572823824023146224494975459868353333808 75
UVM_INFO @ 5190590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12667804215140703689307610802985935737566509707943568015419178709309649341848 78
UVM_INFO @ 1108976040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 44881282465434948725012874679026287535135555350863893793911910468087808427856 1661
UVM_INFO @ 7791043038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71692255368930835839497079406739627762339898461746769496091153307502914158760 802
UVM_INFO @ 775876281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 24033283963852087416199091613452282597310148814516139903807619045033243534563 172
UVM_INFO @ 785335260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 28643521899832922503019229954592385023758745723194306165986625065537265092177 75
UVM_INFO @ 4377066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 99352160886233972829552859783864570625077605598788790210974654963219936278232 234
UVM_INFO @ 807970189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 7688836390889064814545088888052251777493200382661302500780119778830842114600 79
UVM_INFO @ 1068370489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11027531060954942427908450659233367926637623625502558998905583072908921256202 815
UVM_INFO @ 8268617936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 19163276815380937517689685218448764089158801999917288527942835788022862100889 543
UVM_INFO @ 6337966584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 74917245111348226997967555060527127536307390637236309292647762287127236410096 988
UVM_INFO @ 14405968886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1345686904223661936693426158438397071113909938297388471818697849734705810268 1418
UVM_INFO @ 1782472685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 6024290648756920298791803262260209343198388788677508014744516012303845787465 75
UVM_INFO @ 4195855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 100532465717022718407999123964129320651399023873326670069365983154158373589617 1665
UVM_INFO @ 58695303893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 68700935803764771878862489854002228514909860650382198995759778623046075114475 75
UVM_INFO @ 7103360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 31582110832530320668471858502483275544959163801846712850929906676022242917443 75
UVM_INFO @ 1220607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1493207930482033762566648044185812069494679480084227615012614226927836372649 611
UVM_INFO @ 5254899913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 87926030875556240655284175031239177514614170716431487441430391810154991235744 330
UVM_INFO @ 931208605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114526201144892720130463743439677728929255046765798202391770269371175637057630 1261
UVM_INFO @ 16298094277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 67126983188991452393822614842423902784380392643647050011688597252788191067100 806
UVM_INFO @ 8995126590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 80478758394538189675105782621099251316134688652738175820327063247173249464658 78
UVM_INFO @ 1071584356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 85783271977464240717788066906486552543760893092976813173120979521272105059908 2218
UVM_INFO @ 27901868328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 110782065161082041501770987788942182579607350298439045650632900072533377014683 75
UVM_INFO @ 1560929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 110696604931143575158704371884985616840713880149219889292724868271661097680800 76
UVM_INFO @ 1936913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 75326874021098833827573048589053119363529788242215375176534750077686976890572 2747
UVM_INFO @ 13065517630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 48929335263728884082519461835506314772067562802867330448393485923968167679551 75
UVM_INFO @ 1814763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 96790133873783150405105825533892643916199279736842992276908694793820816180395 183
UVM_INFO @ 2327326496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 74982317807798537841306839465487442647388418507998459602202486113047969723391 186
UVM_INFO @ 171412354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 109679135587001036008435630153522844355744611936986877593780166811457796152942 1737
UVM_INFO @ 15769616606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 17581420154095486776939771515791439517872052569808363539716166255198981867432 798
UVM_INFO @ 2353599635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 43860797453434998088635043469577978500740805093132067247973164082600396308682 2132
UVM_INFO @ 8082576162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 73553306654845763822283181932058053992391158648210704642200933186488239285354 76
UVM_INFO @ 55058220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 59214481866589016929068807122497551858888727810441773041352372234028948356110 2391
UVM_INFO @ 14164388856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101717380843849047575772105176934881772870921835097031626215023821241556498445 1058
UVM_INFO @ 2719273426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 89731278589786849454006381242731653074752381559325786144184158998656025139658 1608
UVM_INFO @ 15625019772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 22331334257120335697143161589776964163709391500903608577337598316357717334711 606
UVM_INFO @ 11150102954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done)
gpio_stress_all_with_rand_reset 42584296659757643229605873914466852778931345057706082349863816120343943785342 87
UVM_INFO @ 9700610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6911392714080783767721818083809783108615860426303100472385641922753444716115 303
UVM_INFO @ 2850352394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 55894620554888864324417859582471983077581104689554236194389807794332296846435 80
UVM_INFO @ 140506394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 94744739446649512560570675222267836298070432225568508311575542707326637670707 81
UVM_INFO @ 373680064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 5276666742473379847136848297443303697900103621319199611112767695647711667797 250
UVM_INFO @ 561253586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 44913130184163354834202479997060923842851910691761225287831429354106833653436 246
UVM_INFO @ 1273044472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 89619730287290066429148872679751340066005516685339828280689256490218122776288 80
UVM_INFO @ 4943864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 25284834572932768374442593245587942060683376560710691487167900316118576495235 80
UVM_INFO @ 6980034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 70923981637998537748594394151402793920327554153146345555741289262337821495258 80
UVM_INFO @ 21295585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 34813830150762967044344423369150571907887481777871631060006593707489167159529 84
UVM_INFO @ 342224782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 105395173143271792114297586178430612451111663447730199592940798971812871286334 118
UVM_INFO @ 276638826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 36480097044910638655296383680256521557489551737401177899931563647078957699367 80
UVM_INFO @ 418789798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 108610211366134392314201242041959951555632183766049931023303737680459357553926 80
UVM_INFO @ 3705946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 106643726619031025697494038280398704098159592753987163338428921444402735760839 338
UVM_INFO @ 2072061500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85014721036805590939468826148901233984742489164411528707726781557297829372565 150
UVM_INFO @ 1402437966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 60113656432535119067785873318951874451629436337324999563168461336945047608793 148
UVM_INFO @ 189553678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 42866140120652929347792595914206080154565968361758880930010825707519681111753 81
UVM_INFO @ 276532938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 98244903594506447487869864520255280147965139875147849753454080076147550661087 80
UVM_INFO @ 9300022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 20030945510166882191323233409024036514343997426154070528450413149318079686059 80
UVM_INFO @ 21246347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 109577935702411660959371444184709854703018691805574926112627226587698518820046 83
UVM_INFO @ 6529198774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 98076480441763776901057393853905514885815055256225631773445800775317501738953 80
UVM_INFO @ 12910175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 84069119407802341273456100829948270998519815992697889696280699895573387344226 81
UVM_INFO @ 123565151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 44809882398840738828492778463885297246718390351329874562108106633136036564195 80
UVM_INFO @ 5347916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 47254439283351913187958644283525782048696030432667180751471110007628540092896 80
UVM_INFO @ 20796283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 5154721330764638999955152777775214402077262192431741593644726007687309488267 80
UVM_INFO @ 11215273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 13765908296549468739903585928111863456876484462122079554630585305397123226679 308
UVM_INFO @ 1491522121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
gpio_same_csr_outstanding 60070616276149288341077571290667008272435690479908530600778812564956194544212 77
UVM_INFO @ 148839245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 99524688321345752618006222710555731661009374044910155884449641002620013467770 78
UVM_INFO @ 220138538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 18603958030247586526760312947990328208502973163144859864218199229609366834508 79
UVM_INFO @ 42714187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: *
gpio_tl_intg_err 26621717612381838568294333062971749576714029046749992632872407480166972166771 171
UVM_INFO @ 225685556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: *
gpio_tl_intg_err 113953467521833753129876451061021202176300304273533248765821140127820245548539 169
UVM_INFO @ 62599812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---