Simulation Results: hmac

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.05 %
  • code
  • 99.34 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.96 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.220s 1104.488us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.220s 90.614us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.260s 101.803us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 13.890s 1065.739us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.180s 158.007us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 751.110s 166007.744us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.260s 101.803us 20 20 100.00
hmac_csr_aliasing 7.180s 158.007us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 76.650s 18192.031us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 83.090s 1444.004us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 251.780s 24363.368us 30 30 100.00
hmac_test_sha384_vectors 583.270s 16623.238us 75 75 100.00
hmac_test_sha512_vectors 523.770s 13590.113us 75 75 100.00
hmac_test_hmac256_vectors 15.960s 2933.653us 50 50 100.00
hmac_test_hmac384_vectors 15.990s 345.628us 60 60 100.00
hmac_test_hmac512_vectors 16.720s 1622.658us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 43.110s 873.354us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 722.070s 14577.507us 10 10 100.00
error 10 10 100.00
hmac_error 88.330s 1602.202us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 98.480s 11580.613us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.220s 1104.488us 10 10 100.00
hmac_long_msg 76.650s 18192.031us 10 10 100.00
hmac_back_pressure 83.090s 1444.004us 25 25 100.00
hmac_datapath_stress 722.070s 14577.507us 10 10 100.00
hmac_burst_wr 43.110s 873.354us 50 50 100.00
hmac_stress_all 2423.880s 468662.181us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.220s 1104.488us 10 10 100.00
hmac_long_msg 76.650s 18192.031us 10 10 100.00
hmac_back_pressure 83.090s 1444.004us 25 25 100.00
hmac_datapath_stress 722.070s 14577.507us 10 10 100.00
hmac_wipe_secret 98.480s 11580.613us 10 10 100.00
hmac_test_sha256_vectors 251.780s 24363.368us 30 30 100.00
hmac_test_sha384_vectors 583.270s 16623.238us 75 75 100.00
hmac_test_sha512_vectors 523.770s 13590.113us 75 75 100.00
hmac_test_hmac256_vectors 15.960s 2933.653us 50 50 100.00
hmac_test_hmac384_vectors 15.990s 345.628us 60 60 100.00
hmac_test_hmac512_vectors 16.720s 1622.658us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.220s 1104.488us 10 10 100.00
hmac_long_msg 76.650s 18192.031us 10 10 100.00
hmac_back_pressure 83.090s 1444.004us 25 25 100.00
hmac_datapath_stress 722.070s 14577.507us 10 10 100.00
hmac_burst_wr 43.110s 873.354us 50 50 100.00
hmac_error 88.330s 1602.202us 10 10 100.00
hmac_wipe_secret 98.480s 11580.613us 10 10 100.00
hmac_test_sha256_vectors 251.780s 24363.368us 30 30 100.00
hmac_test_sha384_vectors 583.270s 16623.238us 75 75 100.00
hmac_test_sha512_vectors 523.770s 13590.113us 75 75 100.00
hmac_test_hmac256_vectors 15.960s 2933.653us 50 50 100.00
hmac_test_hmac384_vectors 15.990s 345.628us 60 60 100.00
hmac_test_hmac512_vectors 16.720s 1622.658us 75 75 100.00
hmac_stress_all 2423.880s 468662.181us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2423.880s 468662.181us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.920s 13.803us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.950s 23.281us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.360s 216.061us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.360s 216.061us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.220s 90.614us 5 5 100.00
hmac_csr_rw 1.260s 101.803us 20 20 100.00
hmac_csr_aliasing 7.180s 158.007us 5 5 100.00
hmac_same_csr_outstanding 2.440s 175.934us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.220s 90.614us 5 5 100.00
hmac_csr_rw 1.260s 101.803us 20 20 100.00
hmac_csr_aliasing 7.180s 158.007us 5 5 100.00
hmac_same_csr_outstanding 2.440s 175.934us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.210s 45.177us 5 5 100.00
hmac_tl_intg_err 4.940s 278.102us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.940s 278.102us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.220s 1104.488us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.010s 486.945us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 585.990s 7603.882us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.930s 22.903us 1 1 100.00