Simulation Results

Simulation Results: keymgr

10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.95 %

code
98.97 %

assert
97.72 %

func
91.16 %

line
99.20 %

branch
99.00 %

cond
98.16 %

toggle
98.47 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.57%
V2S		98.44%
V3		48.00%

155/155 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_smoke	34.280s	1471.972us	50	50	100.00
random				50	50	100.00
	keymgr_random	40.440s	2050.421us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_csr_hw_reset	2.010s	52.902us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_csr_bit_bash	16.010s	2688.657us	5	5	100.00
csr_aliasing				5	5	100.00
	keymgr_csr_aliasing	10.270s	379.264us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_csr_mem_rw_with_rand_reset	2.530s	50.645us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
	keymgr_csr_aliasing	10.270s	379.264us	5	5	100.00

759/770 passed

98.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				49	50	98.00
	keymgr_cfg_regwen	77.090s	9870.404us	49	50	98.00
sideload				199	200	99.50
	keymgr_sideload	42.200s	1748.315us	50	50	100.00
	keymgr_sideload_kmac	31.010s	1840.954us	49	50	98.00
	keymgr_sideload_aes	38.220s	24400.708us	50	50	100.00
	keymgr_sideload_otbn	36.270s	1852.608us	50	50	100.00
direct_to_disabled_state				49	50	98.00
	keymgr_direct_to_disabled	26.320s	2324.862us	49	50	98.00
lc_disable				48	50	96.00
	keymgr_lc_disable	10.190s	404.646us	48	50	96.00
kmac_error_response				50	50	100.00
	keymgr_kmac_rsp_err	10.520s	519.751us	50	50	100.00
invalid_sw_input				49	50	98.00
	keymgr_sw_invalid_input	49.420s	4530.023us	49	50	98.00
invalid_hw_input				47	50	94.00
	keymgr_hwsw_invalid_input	23.230s	1049.444us	47	50	94.00
sync_async_fault_cross				49	50	98.00
	keymgr_sync_async_fault_cross	10.510s	891.144us	49	50	98.00
stress_all				49	50	98.00
	keymgr_stress_all	594.730s	39939.780us	49	50	98.00
intr_test				50	50	100.00
	keymgr_intr_test	1.310s	19.597us	50	50	100.00
alert_test				50	50	100.00
	keymgr_alert_test	1.330s	83.319us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_tl_errors	3.810s	130.115us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_tl_errors	3.810s	130.115us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	keymgr_csr_hw_reset	2.010s	52.902us	5	5	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
	keymgr_csr_aliasing	10.270s	379.264us	5	5	100.00
	keymgr_same_csr_outstanding	4.630s	126.346us	20	20	100.00
tl_d_partial_access				50	50	100.00
	keymgr_csr_hw_reset	2.010s	52.902us	5	5	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
	keymgr_csr_aliasing	10.270s	379.264us	5	5	100.00
	keymgr_same_csr_outstanding	4.630s	126.346us	20	20	100.00

V2S

379/385 passed

98.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
tl_intg_err				25	25	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
	keymgr_tl_intg_err	8.050s	273.375us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	4.600s	177.964us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	4.600s	177.964us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	4.600s	177.964us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	4.600s	177.964us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	14.260s	1555.286us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	keymgr_tl_intg_err	8.050s	273.375us	20	20	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	4.600s	177.964us	20	20	100.00
sec_cm_op_config_regwen				49	50	98.00
	keymgr_cfg_regwen	77.090s	9870.404us	49	50	98.00
sec_cm_reseed_config_regwen				70	70	100.00
	keymgr_random	40.440s	2050.421us	50	50	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
sec_cm_sw_binding_config_regwen				70	70	100.00
	keymgr_random	40.440s	2050.421us	50	50	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
sec_cm_max_key_ver_config_regwen				70	70	100.00
	keymgr_random	40.440s	2050.421us	50	50	100.00
	keymgr_csr_rw	1.590s	24.278us	20	20	100.00
sec_cm_lc_ctrl_intersig_mubi				48	50	96.00
	keymgr_lc_disable	10.190s	404.646us	48	50	96.00
sec_cm_constants_consistency				47	50	94.00
	keymgr_hwsw_invalid_input	23.230s	1049.444us	47	50	94.00
sec_cm_intersig_consistency				47	50	94.00
	keymgr_hwsw_invalid_input	23.230s	1049.444us	47	50	94.00
sec_cm_hw_key_sw_noaccess				50	50	100.00
	keymgr_random	40.440s	2050.421us	50	50	100.00
sec_cm_output_keys_ctrl_redun				50	50	100.00
	keymgr_sideload_protect	27.840s	1785.667us	50	50	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_ctrl_fsm_consistency				50	50	100.00
	keymgr_custom_cm	47.250s	3988.633us	50	50	100.00
sec_cm_ctrl_fsm_global_esc				48	50	96.00
	keymgr_lc_disable	10.190s	404.646us	48	50	96.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	47.250s	3988.633us	50	50	100.00
sec_cm_kmac_if_done_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	47.250s	3988.633us	50	50	100.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	47.250s	3988.633us	50	50	100.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	12.510s	2043.581us	5	5	100.00
sec_cm_ctrl_key_integrity				50	50	100.00
	keymgr_custom_cm	47.250s	3988.633us	50	50	100.00

24/50 passed

48.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				24	50	48.00
	keymgr_stress_all_with_rand_reset	24.330s	1793.621us	24	50	48.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	keymgr_stress_all_with_rand_reset	93055605747191899178348107568268684621054267150774818846969109566502623597905	410	UVM_INFO @ 1381142550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	12347043005288011187948919576586269924022896967769511014315238517159823020401	381	UVM_INFO @ 196654258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	42697312894962525513313739707422937238713526692159749441087102700110509036400	102	UVM_INFO @ 446244120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	28541583839195708002841355835352948708700973675355348948621252473371550530453	541	UVM_INFO @ 572722651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	68229990773878966553148308344908250150216119341367107305706149800734432659063	138	UVM_INFO @ 898765836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	5748493853514705212582343985629681966145962033558040760750812553391964504234	416	UVM_INFO @ 673295117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	21750933286487122081598437048866096167822502672153327535824551711904653834577	237	UVM_INFO @ 262749549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	35471266538374905724291053068730317288730784844216156564431116289369398933939	173	UVM_INFO @ 1007481174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	48331630780727456275806027631299684268864545752469150723036524734183643381629	122	UVM_INFO @ 109455754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	95225527487174872446549148911978853954005898000748001439812314787018205666802	183	UVM_INFO @ 120569238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	15719208931056555646372163047243305955194461048820568154338707447598942432993	1080	UVM_INFO @ 569857744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	38450301345613108200907479054048462999994686575180119712869427590937117633171	1134	UVM_INFO @ 418280600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	3238681911002559227348277275930845227248318574461328184088691378373527881777	138	UVM_INFO @ 957663832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	101725516666608086732173512424876186816418322764827035567142649803274926463477	154	UVM_INFO @ 1359830262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	98177736152996136847880403353684923366081621634880896546510952186745498225942	1222	UVM_INFO @ 1758941534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	106272482756760759840534655064365520246120392928014322946621389535716502030784	96	UVM_INFO @ 868692847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	9949268793974084252248122730928603386672592266551423242411297951383993833182	306	UVM_INFO @ 291124094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	33512822899519604731559314445762254281127838814241026894198499274502234888513	986	UVM_INFO @ 1476223467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	10614984098689157249247754471606740133864524303491851050504242719757361039102	315	UVM_INFO @ 481057901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	102266961545502823368043643166543198106627090796691358724476751327170153534549	465	UVM_INFO @ 390759054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	5814955854536487700783069488765804912346586687533240329538918801876548302814	399	UVM_INFO @ 480116573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	63039606293871165234079038164561258900931985864194340286121375364030694952738	610	UVM_INFO @ 544859497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	70559234455088067412902733422330089384560088069960994896296035124260710669845	585	UVM_INFO @ 1623987780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	40468430746746826505215753340592832312471428412350435204435293250936325177226	215	UVM_INFO @ 1678798240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	4622138873567564905662032364462900708154088468750107143368895039677152337893	239	UVM_INFO @ 234666921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_operation_err triggered unexpectedly
	keymgr_hwsw_invalid_input	54646743337674366860617584797528977351436759868050469293771478941232654479434	227	UVM_INFO @ 29422088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_hwsw_invalid_input	7893003665472488278945131909987171977835136993197825677568594700049432089479	371	UVM_INFO @ 91231427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_hwsw_invalid_input	4799059792920620491419166271627997949639442648178193814016368233351211166094	264	UVM_INFO @ 42170094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
	keymgr_stress_all	101716073084116488192726749051294930925566384346971842179731958771077330026646	877	UVM_INFO @ 220416921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_sideload_kmac	112385060232628490456303894130950058390119748700482159651358466262199305346859	91	UVM_INFO @ 7337338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_sw_invalid_input	44882964269735444457542512868935661417978144436035349206891523248022591902879	85	UVM_INFO @ 7878625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_direct_to_disabled	97083767253308323997004901212362132889260908017463578817688953361174155565039	187	UVM_INFO @ 126884358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	79868528169943814955937697628001785767946426563644102462218585869235211686093	297	UVM_INFO @ 37343339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_cfg_regwen	32470808650134014544500753895715434457801285405925569671406280712858096772352	182	UVM_INFO @ 20519337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] \|\| act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [] vs [*])
	keymgr_sync_async_fault_cross	41920351362564307376452298193334150562157250869540157834683013614532132279965	178	UVM_INFO @ 219718978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[], act_key.key[]} !== keys_a_array[state][cdi][dest] (* [] vs [*]) KMAC key at state StDisabled for Attestation Kmac
	keymgr_lc_disable	51820477282948697714832110107143783662438094358581023472754373564889047483495	288	UVM_INFO @ 50019255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share0_output_
	keymgr_lc_disable	91941501363536523458973964493050518948829108291638462728029902081401463442254	277	UVM_INFO @ 102376057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---