| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| keymgr_dpe_smoke | 185.970s | 20072.039us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.210s | 21.112us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_csr_rw | 1.430s | 97.349us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 16.540s | 3552.441us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 4.740s | 931.335us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 1.980s | 63.781us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| keymgr_dpe_csr_rw | 1.430s | 97.349us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.740s | 931.335us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 50 | 50 | 100.00 | |||
| keymgr_dpe_intr_test | 1.360s | 20.189us | 50 | 50 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| keymgr_dpe_alert_test | 1.590s | 200.796us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| keymgr_dpe_tl_errors | 4.430s | 128.459us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| keymgr_dpe_tl_errors | 4.430s | 128.459us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.210s | 21.112us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_rw | 1.430s | 97.349us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.740s | 931.335us | 5 | 5 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 3.240s | 320.857us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.210s | 21.112us | 5 | 5 | 100.00 | |
| keymgr_dpe_csr_rw | 1.430s | 97.349us | 20 | 20 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.740s | 931.335us | 5 | 5 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 3.240s | 320.857us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| keymgr_dpe_sec_cm | 15.980s | 3563.253us | 5 | 5 | 100.00 | |
| keymgr_dpe_tl_intg_err | 5.920s | 233.209us | 20 | 20 | 100.00 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.120s | 129.322us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.120s | 129.322us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.120s | 129.322us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 3.120s | 129.322us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 6.220s | 2915.798us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 15.980s | 3563.253us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| keymgr_dpe_sec_cm | 15.980s | 3563.253us | 5 | 5 | 100.00 | |