Simulation Results: kmac/masked

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 94.25 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
100.00%
V2
99.74%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 84.540s 39316.764us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.470s 85.630us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.560s 55.315us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 21.380s 5338.970us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.170s 270.042us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.280s 322.751us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.560s 55.315us 20 20 100.00
kmac_csr_aliasing 8.170s 270.042us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.110s 43.765us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.790s 71.374us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3572.150s 260590.291us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1344.570s 38293.815us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 41.200s 3416.431us 5 5 100.00
kmac_test_vectors_sha3_256 38.430s 14985.038us 5 5 100.00
kmac_test_vectors_sha3_384 1593.550s 213844.366us 5 5 100.00
kmac_test_vectors_sha3_512 1124.310s 86797.862us 5 5 100.00
kmac_test_vectors_shake_128 2795.880s 461838.773us 5 5 100.00
kmac_test_vectors_shake_256 1743.280s 345176.295us 5 5 100.00
kmac_test_vectors_kmac 3.820s 413.787us 5 5 100.00
kmac_test_vectors_kmac_xof 3.800s 141.387us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 441.140s 15501.266us 50 50 100.00
app 50 50 100.00
kmac_app 399.530s 50248.557us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 360.840s 72705.500us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 363.070s 235889.892us 50 50 100.00
error 50 50 100.00
kmac_error 453.570s 30514.830us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 18.850s 4218.176us 49 50 98.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.190s 963.435us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 53.670s 5848.274us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 47.730s 1353.323us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 70.240s 6208.222us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 39.490s 887.413us 50 50 100.00
stress_all 49 50 98.00
kmac_stress_all 3555.000s 120343.083us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 1.210s 26.240us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.240s 23.604us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.720s 645.654us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.720s 645.654us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.470s 85.630us 5 5 100.00
kmac_csr_rw 1.560s 55.315us 20 20 100.00
kmac_csr_aliasing 8.170s 270.042us 5 5 100.00
kmac_same_csr_outstanding 3.230s 221.374us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.470s 85.630us 5 5 100.00
kmac_csr_rw 1.560s 55.315us 20 20 100.00
kmac_csr_aliasing 8.170s 270.042us 5 5 100.00
kmac_same_csr_outstanding 3.230s 221.374us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.920s 194.105us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.920s 194.105us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.920s 194.105us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.920s 194.105us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.490s 483.690us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 92.640s 11115.269us 5 5 100.00
kmac_tl_intg_err 7.040s 1622.679us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 7.040s 1622.679us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 39.490s 887.413us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 84.540s 39316.764us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 441.140s 15501.266us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.920s 194.105us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 92.640s 11115.269us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 92.640s 11115.269us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 92.640s 11115.269us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 84.540s 39316.764us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 39.490s 887.413us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 92.640s 11115.269us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 323.120s 11733.462us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 84.540s 39316.764us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 129.330s 4842.208us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 95570299297164737100792591865339967825531164779170590099798502707780972923464 239
UVM_INFO @ 1246313615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 49144084762703263886404596956388433240269048410750037018362379737365163028835 313
UVM_INFO @ 2230329115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 5548664725924415882629878823431127807199439111692919883739531227350842805576 265
UVM_INFO @ 13296086310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!
kmac_key_error 107354275793384462656493669764916245952581138060397983512766784637146279348273 103
UVM_INFO @ 2464173361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 73061450707164131793331623024232216140052565297325372991867423819401402917578 80
UVM_INFO @ 70455527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---