Simulation Results

Simulation Results: kmac/unmasked

10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.53 %

code
92.01 %

assert
97.90 %

func
96.68 %

line
97.56 %

branch
95.85 %

cond
94.75 %

toggle
100.00 %

FSM
71.90 %

Validation stages

V1		100.00%
V2		98.31%
V2S		99.56%
V3		70.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	kmac_smoke	64.320s	11933.579us	50	50	100.00
csr_hw_reset				5	5	100.00
	kmac_csr_hw_reset	1.470s	162.378us	5	5	100.00
csr_rw				20	20	100.00
	kmac_csr_rw	1.520s	34.992us	20	20	100.00
csr_bit_bash				5	5	100.00
	kmac_csr_bit_bash	10.420s	748.151us	5	5	100.00
csr_aliasing				5	5	100.00
	kmac_csr_aliasing	9.890s	1583.407us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	kmac_csr_mem_rw_with_rand_reset	3.210s	169.478us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	kmac_csr_rw	1.520s	34.992us	20	20	100.00
	kmac_csr_aliasing	9.890s	1583.407us	5	5	100.00
mem_walk				5	5	100.00
	kmac_mem_walk	1.140s	30.736us	5	5	100.00
mem_partial_access				5	5	100.00
	kmac_mem_partial_access	1.850s	132.923us	5	5	100.00

757/770 passed

98.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				50	50	100.00
	kmac_long_msg_and_output	3454.440s	557183.893us	50	50	100.00
burst_write				50	50	100.00
	kmac_burst_write	765.800s	174677.381us	50	50	100.00
test_vectors				40	40	100.00
	kmac_test_vectors_sha3_224	42.200s	2643.869us	5	5	100.00
	kmac_test_vectors_sha3_256	1397.750s	33100.236us	5	5	100.00
	kmac_test_vectors_sha3_384	1417.710s	135396.454us	5	5	100.00
	kmac_test_vectors_sha3_512	939.430s	388478.331us	5	5	100.00
	kmac_test_vectors_shake_128	2298.860s	432953.202us	5	5	100.00
	kmac_test_vectors_shake_256	1914.910s	596554.078us	5	5	100.00
	kmac_test_vectors_kmac	2.880s	81.015us	5	5	100.00
	kmac_test_vectors_kmac_xof	3.150s	522.903us	5	5	100.00
sideload				50	50	100.00
	kmac_sideload	379.670s	38055.395us	50	50	100.00
app				50	50	100.00
	kmac_app	324.390s	261464.558us	50	50	100.00
app_with_partial_data				10	10	100.00
	kmac_app_with_partial_data	260.890s	57196.100us	10	10	100.00
entropy_refresh				50	50	100.00
	kmac_entropy_refresh	334.270s	164517.468us	50	50	100.00
error				49	50	98.00
	kmac_error	394.880s	38431.457us	49	50	98.00
key_error				50	50	100.00
	kmac_key_error	14.310s	19484.920us	50	50	100.00
sideload_invalid				38	50	76.00
	kmac_sideload_invalid	113.350s	10098.730us	38	50	76.00
edn_timeout_error				20	20	100.00
	kmac_edn_timeout_error	33.880s	1530.761us	20	20	100.00
entropy_mode_error				20	20	100.00
	kmac_entropy_mode_error	51.500s	31893.376us	20	20	100.00
entropy_ready_error				10	10	100.00
	kmac_entropy_ready_error	64.680s	8144.619us	10	10	100.00
lc_escalation				50	50	100.00
	kmac_lc_escalation	30.880s	749.621us	50	50	100.00
stress_all				50	50	100.00
	kmac_stress_all	1994.790s	80775.893us	50	50	100.00
intr_test				50	50	100.00
	kmac_intr_test	1.190s	24.012us	50	50	100.00
alert_test				50	50	100.00
	kmac_alert_test	1.190s	22.431us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	kmac_tl_errors	4.500s	300.566us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	kmac_tl_errors	4.500s	300.566us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	kmac_csr_hw_reset	1.470s	162.378us	5	5	100.00
	kmac_csr_rw	1.520s	34.992us	20	20	100.00
	kmac_csr_aliasing	9.890s	1583.407us	5	5	100.00
	kmac_same_csr_outstanding	2.560s	122.386us	20	20	100.00
tl_d_partial_access				50	50	100.00
	kmac_csr_hw_reset	1.470s	162.378us	5	5	100.00
	kmac_csr_rw	1.520s	34.992us	20	20	100.00
	kmac_csr_aliasing	9.890s	1583.407us	5	5	100.00
	kmac_same_csr_outstanding	2.560s	122.386us	20	20	100.00

V2S

224/225 passed

99.56 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	kmac_shadow_reg_errors	3.640s	250.072us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	kmac_shadow_reg_errors	3.640s	250.072us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	kmac_shadow_reg_errors	3.640s	250.072us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	kmac_shadow_reg_errors	3.640s	250.072us	20	20	100.00
shadow_reg_update_error_with_csr_rw				19	20	95.00
	kmac_shadow_reg_errors_with_csr_rw	6.220s	793.143us	19	20	95.00
tl_intg_err				25	25	100.00
	kmac_sec_cm	78.300s	6825.731us	5	5	100.00
	kmac_tl_intg_err	5.340s	198.744us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	kmac_tl_intg_err	5.340s	198.744us	20	20	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	kmac_lc_escalation	30.880s	749.621us	50	50	100.00
sec_cm_sw_key_key_masking				50	50	100.00
	kmac_smoke	64.320s	11933.579us	50	50	100.00
sec_cm_key_sideload				50	50	100.00
	kmac_sideload	379.670s	38055.395us	50	50	100.00
sec_cm_cfg_shadowed_config_shadow				20	20	100.00
	kmac_shadow_reg_errors	3.640s	250.072us	20	20	100.00
sec_cm_fsm_sparse				5	5	100.00
	kmac_sec_cm	78.300s	6825.731us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	kmac_sec_cm	78.300s	6825.731us	5	5	100.00
sec_cm_packer_ctr_redun				5	5	100.00
	kmac_sec_cm	78.300s	6825.731us	5	5	100.00
sec_cm_cfg_shadowed_config_regwen				50	50	100.00
	kmac_smoke	64.320s	11933.579us	50	50	100.00
sec_cm_fsm_global_esc				50	50	100.00
	kmac_lc_escalation	30.880s	749.621us	50	50	100.00
sec_cm_fsm_local_esc				5	5	100.00
	kmac_sec_cm	78.300s	6825.731us	5	5	100.00
sec_cm_absorbed_ctrl_mubi				10	10	100.00
	kmac_mubi	205.760s	19856.374us	10	10	100.00
sec_cm_sw_cmd_ctrl_sparse				50	50	100.00
	kmac_smoke	64.320s	11933.579us	50	50	100.00

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				7	10	70.00
	kmac_stress_all_with_rand_reset	254.790s	4161.508us	7	10	70.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	kmac_sideload_invalid	57677024538276496500419583400225528161696756649538395770132014051934139014058	79	UVM_INFO @ 10024840541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	65474287197446418024777471879993336830027332001194886408871477695629031055547	79	UVM_INFO @ 10075984518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [] vs [*])
	kmac_stress_all_with_rand_reset	97813680627849313609697735872253099836851445894203447304049054973335511101539	242	UVM_INFO @ 12931665533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	kmac_stress_all_with_rand_reset	47376637830192106132974086972028006326987210107222074546901017101425897424649	231	UVM_INFO @ 12985506177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	32730449209551310872192939169658068551592363679041251999332956688037712938032	257	UVM_INFO @ 8446001827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=4)
	kmac_sideload_invalid	53003397194141951291716298989079093386391142468999606336620204862235740456400	80	UVM_INFO @ 10138868262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=15)
	kmac_sideload_invalid	30791515952925842859729321525954375412526611491555778176266521156812032694058	92	UVM_INFO @ 10118343512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=11)
	kmac_sideload_invalid	3392554180327563543201464953592315088571742945108575389213627078921702234858	87	UVM_INFO @ 10077334845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=9)
	kmac_sideload_invalid	37601267556399036799965030322236286949610621700932715820594563321891055408239	88	UVM_INFO @ 10059374419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	33235620944326623055773735432527660489420316312310399526894829514597479331357	86	UVM_INFO @ 10139970727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: kmac_reg_block.prefix_ reset value: *
	kmac_shadow_reg_errors_with_csr_rw	49207559712040696774431885977625624556930854227075599711747634918615105160874	142	UVM_INFO @ 23827209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=2)
	kmac_sideload_invalid	70759967352461167719537781872787455082248750497622835762718916181840529543066	78	UVM_INFO @ 10035591767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	45853959354365956132540585492055535014114582735548663272395344989624479502572	78	UVM_INFO @ 10018533235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=5)
	kmac_sideload_invalid	22236119947180526413515726941346146565473082564577127373121326581031540385621	81	UVM_INFO @ 10124735137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	112673708315885556995343909451785934156193845305453629768386246139087350459618	82	UVM_INFO @ 10064284663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	kmac_error	95796408659415836098554117632797223869327459965818241819910857178828397559286	256	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=13)
	kmac_sideload_invalid	6157422671941273334895551072757930730833556444721605739672406909475461676158	90	UVM_INFO @ 10098729947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---