Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.66 %
  • code
  • 88.96 %
  • assert
  • 95.99 %
  • func
  • 96.04 %
  • line
  • 97.90 %
  • branch
  • 96.99 %
  • cond
  • 82.21 %
  • toggle
  • 91.35 %
  • FSM
  • 76.36 %
Validation stages
V1
100.00%
V2
99.59%
V2S
99.72%
V3
46.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 7.580s 113.801us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.550s 96.928us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.440s 57.170us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.950s 52.605us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 162.165us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.970s 27.928us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.440s 57.170us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 162.165us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 7.640s 96.263us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.160s 361.424us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.290s 42.831us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.540s 291.081us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 17.130s 7882.685us 50 50 100.00
security_escalation 260 260 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_prog_failure 4.540s 291.081us 50 50 100.00
lc_ctrl_errors 17.130s 7882.685us 50 50 100.00
lc_ctrl_security_escalation 13.030s 2303.443us 50 50 100.00
lc_ctrl_jtag_state_failure 59.030s 5868.954us 20 20 100.00
lc_ctrl_jtag_prog_failure 24.560s 4682.855us 20 20 100.00
lc_ctrl_jtag_errors 47.360s 22129.789us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 11.480s 1955.615us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.690s 1071.257us 20 20 100.00
lc_ctrl_jtag_prog_failure 24.560s 4682.855us 20 20 100.00
lc_ctrl_jtag_errors 47.360s 22129.789us 20 20 100.00
lc_ctrl_jtag_access 20.700s 1170.495us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.860s 1572.713us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.470s 131.330us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.670s 121.149us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 35.580s 4324.433us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 16.520s 940.605us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.710s 24.343us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.860s 353.484us 10 10 100.00
lc_ctrl_jtag_alert_test 2.090s 86.415us 10 10 100.00
jtag_priority 8 10 80.00
lc_ctrl_jtag_priority 29.780s 30220.042us 8 10 80.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.380s 36.401us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 471.880s 33941.169us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.980s 552.606us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.780s 450.581us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.780s 450.581us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.550s 96.928us 5 5 100.00
lc_ctrl_csr_rw 1.440s 57.170us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 162.165us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.840s 54.631us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.550s 96.928us 5 5 100.00
lc_ctrl_csr_rw 1.440s 57.170us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 162.165us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.840s 54.631us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
lc_ctrl_tl_intg_err 3.580s 851.327us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.580s 851.327us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.160s 361.424us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 13.260s 1197.446us 50 50 100.00
lc_ctrl_sec_cm 10.930s 244.093us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 13.030s 2303.443us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 7.640s 96.263us 50 50 100.00
lc_ctrl_jtag_state_post_trans 22.690s 1071.257us 20 20 100.00
sec_cm_intersig_mubi 49 50 98.00
lc_ctrl_sec_mubi 12.020s 648.552us 49 50 98.00
sec_cm_token_valid_ctrl_mubi 49 50 98.00
lc_ctrl_sec_mubi 12.020s 648.552us 49 50 98.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 15.520s 576.029us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.480s 792.441us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 12.480s 792.441us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 50 46.00
lc_ctrl_stress_all_with_rand_reset 148.700s 10322.568us 23 50 46.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 3427571840136036377469693611911166441934610186314339053030359138891540852856 4537
UVM_INFO @ 3064846218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14956746973442133035057554090010070843813609944905964762234245255483614192697 3186
UVM_INFO @ 3489913801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 88715304766083007121096723761790710764849241317919978236117953090606633913860 7838
UVM_INFO @ 2609960159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89635133684273485919692508720760627594109232761590332593396748223498756844119 4134
UVM_INFO @ 2491297331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27828902109860460705190669692998562688582059267176011796121702054301340211161 203
UVM_INFO @ 779897731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64733893587098394879913738094489682262220269100448167923670604732866433660356 3227
UVM_INFO @ 11029549799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46406794087026249589670569246120579062960100668602027889936615920470127695608 3474
UVM_INFO @ 2848296319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100680171476433432714625938352844940182514614346569200138986352771579572637969 776
UVM_INFO @ 1936866167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82589469627117225320504098662287713425105397996023260412321327389482319806362 825
UVM_INFO @ 702802118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24355635953674995551020660619383002620497721773741883554118583323053683246076 203
UVM_INFO @ 110608018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87326587015026307032221671291918112037556818610988829717162374678041476116030 8982
UVM_INFO @ 4546911296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13030107014259894112391721243966078290368180527509496656879342411333406282962 1483
UVM_INFO @ 3334638655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50373173359338338478529999795279636475462165012399049520326916949571588192009 1673
UVM_INFO @ 2275390980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73376332752306134323469569417456879640452356110444721036758267846683499276580 204
UVM_INFO @ 302975360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76492352243590284548656898529509724971768630231946260753378927430122757986229 651
UVM_INFO @ 9763152323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67542794929698303886870216107042896407688101407071895662463455138155435396269 524
UVM_INFO @ 916113409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10821680098864936293533664315759897456460152211245527113356108503247688080311 8176
UVM_INFO @ 7493328392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81211917730228725802946050102235129664074011825395618153829149317542860933465 3576
UVM_INFO @ 1863691298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89034214748268371511220685519367223662392685794350322790912982432120809030007 8804
UVM_INFO @ 1051880965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85207756630919219847717169701731746765881329852113781328284662767259195316953 934
UVM_INFO @ 3976941072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85720568797694665246438093495168547544311895193646595612237430771765766162619 4427
UVM_INFO @ 1915198312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79625418848014300947498755783320062570680584424770731335649371878014135155979 942
UVM_INFO @ 16212679516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76088832072288874600620440188227077582135675042539727029081992162954380056851 15586
UVM_INFO @ 6209491757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5324616796195382734128972089329180539207127708903433363479748148068731574534 16263
UVM_INFO @ 2001986751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52937476159628247303988221483573982645357562013972599546821158335856611261794 150
UVM_INFO @ 389514372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2654784615397565176460323668993320772246990122965291274234153632037714129546 216
UVM_INFO @ 720476979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!
lc_ctrl_jtag_priority 94149410726083778831460091295265355342961719308875927566119027409024179709353 148
UVM_INFO @ 10012895658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 71583750198772302923978052229338986215047594427275831069347364192493113225713 6661
UVM_INFO @ 13570872300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:135) [lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim
lc_ctrl_jtag_priority 82735617536225993761553526666837751142902706853951822341883996923384660940511 148
UVM_INFO @ 30220042301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all 70148129362638051817359922659950263955985902187106089535867474847736932490748 6696
UVM_INFO @ 1724349808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_sec_mubi_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_sec_mubi 48326533009383450251318512669692224730573302761973102513547072780930901661232 685
UVM_INFO @ 194725980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---