Simulation Results: otbn

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 96.72 %
  • assert
  • 96.85 %
  • func
  • 100.00 %
  • block
  • 99.48 %
  • line
  • 99.65 %
  • branch
  • 93.41 %
  • toggle
  • 93.83 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.53%
V3
30.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 79.884us 1 1 100.00
single_binary 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 8.000s 34.198us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 15.039us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 10.000s 355.143us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 8.000s 37.399us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 145.836us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 15.039us 20 20 100.00
otbn_csr_aliasing 8.000s 37.399us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 132.000s 21594.680us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 49.000s 9199.818us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 40.000s 144.253us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 51.000s 663.574us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 104.000s 315.615us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 124.000s 1072.599us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 98.000s 1551.136us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 8.000s 29.220us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 89.000s 1464.536us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 18.681us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 8.000s 51.375us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 10.000s 52.503us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 10.000s 52.503us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 8.000s 34.198us 5 5 100.00
otbn_csr_rw 8.000s 15.039us 20 20 100.00
otbn_csr_aliasing 8.000s 37.399us 5 5 100.00
otbn_same_csr_outstanding 7.000s 37.666us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 8.000s 34.198us 5 5 100.00
otbn_csr_rw 8.000s 15.039us 20 20 100.00
otbn_csr_aliasing 8.000s 37.399us 5 5 100.00
otbn_same_csr_outstanding 7.000s 37.666us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 15.000s 47.285us 10 10 100.00
otbn_dmem_err 16.000s 79.584us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 9.000s 230.263us 5 5 100.00
otbn_controller_ispr_rdata_err 14.000s 127.346us 5 5 100.00
otbn_mac_bignum_acc_err 8.000s 65.610us 5 5 100.00
otbn_urnd_err 8.000s 46.956us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 18.231us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 23.041us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 6.000s 24.256us 8 10 80.00
tl_intg_err 25 25 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
otbn_tl_intg_err 57.000s 332.631us 20 20 100.00
passthru_mem_tl_intg_err 17 20 85.00
otbn_passthru_mem_tl_intg_err 56.000s 218.780us 17 20 85.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 79.884us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 16.000s 79.584us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 15.000s 47.285us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 57.000s 332.631us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 98.000s 1551.136us 60 60 100.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 15.000s 47.285us 10 10 100.00
otbn_dmem_err 16.000s 79.584us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 29.220us 5 5 100.00
otbn_illegal_mem_acc 7.000s 18.231us 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 15.000s 47.285us 10 10 100.00
otbn_dmem_err 16.000s 79.584us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 29.220us 5 5 100.00
otbn_illegal_mem_acc 7.000s 18.231us 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 98.000s 1551.136us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 15.000s 47.285us 10 10 100.00
otbn_dmem_err 16.000s 79.584us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 29.220us 5 5 100.00
otbn_illegal_mem_acc 7.000s 18.231us 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 11.000s 24.804us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 36.421us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 55.000s 119.683us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 55.000s 119.683us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 8.000s 36.683us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 16.000s 106.161us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 18.000s 803.984us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 18.000s 803.984us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 20.000s 54.010us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 104.000s 315.615us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 11.000s 30.394us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 341.000s 1530.275us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 221.000s 1200.102us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 965.000s 10289.084us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 60.091us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 40529887479973577640503228100090121318649227824963820442026783379457759378671 183
UVM_INFO @ 540084052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 13921617977513987027785706853605806680759478284319024386955134566706207361668 182
UVM_INFO @ 869454992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 32216614077713043612440200759769106978698166922742044633593942539932235355783 206
UVM_INFO @ 472363287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 101581003268696766124990544699383654737603258103725977284670934685150451038649 169
UVM_INFO @ 1017021725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 107287759477020897535204998591545202656275594869050490621336344466933015553658 151
UVM_INFO @ 690512811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 115278258477642009982025996065166229464105376603610312868625685971484102743786 226
UVM_INFO @ 11199127261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed
otbn_partial_wipe 38559874162956589555299139859001652165230587752174453242268493943605037224845 117
UVM_ERROR @ 39032418 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 39032418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 115020952495483316028755239164875586851637022573700941697328477267333351688517 106
UVM_INFO @ 140758764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 36734873649413578850728349414446828867849838028091867271128778313470218428778 306
UVM_INFO @ 264319999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 89165108738410548617853297743343051242634906674902992686961858645534575132770 91
UVM_INFO @ 170118143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 34390867036894660470608944165687018115148817944997169288984221641723189264349 116
UVM_INFO @ 10071291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 105445311864335605162511454985105317517396445164442032250508525174352255370187 96
UVM_INFO @ 39943630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---