Simulation Results: rom_ctrl/32kb

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.10%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.630s 180.983us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 6.710s 1021.032us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 5.780s 1036.057us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.480s 166.534us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.680s 2083.571us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.710s 176.242us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 5.780s 1036.057us 20 20 100.00
rom_ctrl_csr_aliasing 5.680s 2083.571us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 7.470s 2276.749us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.380s 195.473us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.240s 567.127us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 24.710s 1340.080us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.870s 303.399us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 6.520s 813.024us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 12.400s 234.856us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 12.400s 234.856us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.710s 1021.032us 5 5 100.00
rom_ctrl_csr_rw 5.780s 1036.057us 20 20 100.00
rom_ctrl_csr_aliasing 5.680s 2083.571us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.700s 795.134us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.710s 1021.032us 5 5 100.00
rom_ctrl_csr_rw 5.780s 1036.057us 20 20 100.00
rom_ctrl_csr_aliasing 5.680s 2083.571us 5 5 100.00
rom_ctrl_same_csr_outstanding 6.700s 795.134us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.460s 840.941us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 219.960s 2306.015us 5 5 100.00
rom_ctrl_tl_intg_err 58.460s 381.139us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 219.960s 2306.015us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 219.960s 2306.015us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 219.960s 2306.015us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 219.960s 2306.015us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.630s 180.983us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.630s 180.983us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.630s 180.983us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 58.460s 381.139us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
rom_ctrl_kmac_err_chk 8.870s 303.399us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 105.740s 50417.034us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.460s 840.941us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 219.960s 2306.015us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 573.950s 27377.054us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 89224485616184547792483340837731970388849660109917580877175312645689619825318 78
UVM_INFO @ 97144310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 16864526909124148308779114990255571246742282968644245461351317541801388418460 99
UVM_INFO @ 31601602885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---