Simulation Results: rstmgr

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.55 %
  • code
  • 99.53 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.32 %
  • toggle
  • 99.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.46%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.900s 74.654us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.730s 91.719us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.230s 36.913us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 4.130s 175.449us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.070s 54.736us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.310s 95.971us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.230s 36.913us 20 20 100.00
rstmgr_csr_aliasing 2.070s 54.736us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 2.100s 147.747us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.430s 44.264us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.500s 88.971us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 9.180s 802.655us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 9.180s 802.655us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 9.180s 802.655us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 9.180s 802.655us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 55.030s 5547.307us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.620s 64.858us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.080s 76.570us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.080s 76.570us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.730s 91.719us 5 5 100.00
rstmgr_csr_rw 1.230s 36.913us 20 20 100.00
rstmgr_csr_aliasing 2.070s 54.736us 5 5 100.00
rstmgr_same_csr_outstanding 1.820s 75.675us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.730s 91.719us 5 5 100.00
rstmgr_csr_rw 1.230s 36.913us 20 20 100.00
rstmgr_csr_aliasing 2.070s 54.736us 5 5 100.00
rstmgr_same_csr_outstanding 1.820s 75.675us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 32.870s 6758.501us 5 5 100.00
rstmgr_tl_intg_err 20.890s 2341.925us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 32.870s 6758.501us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 32.870s 6758.501us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 20.890s 2341.925us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.660s 59.439us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 47 50 94.00
rstmgr_leaf_rst_cnsty 6.120s 471.134us 47 50 94.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 3.470s 291.120us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 32.870s 6758.501us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.230s 36.913us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.230s 36.913us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:*
rstmgr_leaf_rst_cnsty 9978398328381912086093949343806230669619930803669809156881963070284454140183 142
UVM_INFO @ 316494808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 33932682791976597837046021144093954634974525561002602171343282207671671897547 131
UVM_INFO @ 305138886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rstmgr_leaf_rst_cnsty 54131982958344122637958791696386361224863936500939303910832120772648749070745 114
UVM_INFO @ 191471710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---