Simulation Results: rv_dm/use_dmi_interface

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.55 %
  • code
  • 75.32 %
  • assert
  • 96.32 %
  • func
  • 67.00 %
  • line
  • 91.37 %
  • branch
  • 76.50 %
  • cond
  • 78.41 %
  • toggle
  • 74.06 %
  • FSM
  • 56.25 %
Validation stages
V1
98.89%
V2
55.12%
V2S
95.56%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rv_dm_smoke 2.720s 1917.126us 2 2 100.00
jtag_dtm_csr_hw_reset 5 5 100.00
rv_dm_jtag_dtm_csr_hw_reset 2.530s 730.846us 5 5 100.00
jtag_dtm_csr_rw 20 20 100.00
rv_dm_jtag_dtm_csr_rw 3.920s 903.669us 20 20 100.00
jtag_dtm_csr_bit_bash 5 5 100.00
rv_dm_jtag_dtm_csr_bit_bash 121.320s 41684.247us 5 5 100.00
jtag_dtm_csr_aliasing 5 5 100.00
rv_dm_jtag_dtm_csr_aliasing 2.800s 1303.161us 5 5 100.00
jtag_dmi_csr_hw_reset 5 5 100.00
rv_dm_jtag_dmi_csr_hw_reset 50.670s 23458.732us 5 5 100.00
jtag_dmi_csr_rw 20 20 100.00
rv_dm_jtag_dmi_csr_rw 20.000s 9748.334us 20 20 100.00
jtag_dmi_csr_bit_bash 20 20 100.00
rv_dm_jtag_dmi_csr_bit_bash 67.560s 42273.851us 20 20 100.00
jtag_dmi_csr_aliasing 5 5 100.00
rv_dm_jtag_dmi_csr_aliasing 137.340s 61406.277us 5 5 100.00
jtag_dmi_cmderr_busy 2 2 100.00
rv_dm_cmderr_busy 2.330s 872.886us 2 2 100.00
jtag_dmi_cmderr_not_supported 2 2 100.00
rv_dm_cmderr_not_supported 1.320s 299.642us 2 2 100.00
cmderr_exception 2 2 100.00
rv_dm_cmderr_exception 1.470s 673.084us 2 2 100.00
mem_tl_access_resuming 0 2 0.00
rv_dm_mem_tl_access_resuming 2.790s 479.737us 0 2 0.00
mem_tl_access_halted 2 2 100.00
rv_dm_mem_tl_access_halted 2.360s 512.624us 2 2 100.00
cmderr_halt_resume 2 2 100.00
rv_dm_cmderr_halt_resume 2.600s 967.147us 2 2 100.00
dataaddr_rw_access 2 2 100.00
rv_dm_dataaddr_rw_access 1.330s 288.552us 2 2 100.00
halt_resume 8 8 100.00
rv_dm_halt_resume_whereto 2.010s 291.078us 8 8 100.00
progbuf_busy 2 2 100.00
rv_dm_cmderr_busy 2.330s 872.886us 2 2 100.00
abstractcmd_status 2 2 100.00
rv_dm_abstractcmd_status 0.890s 81.228us 2 2 100.00
progbuf_read_write_execute 2 2 100.00
rv_dm_progbuf_read_write_execute 1.400s 1355.188us 2 2 100.00
progbuf_exception 2 2 100.00
rv_dm_cmderr_exception 1.470s 673.084us 2 2 100.00
rom_read_access 2 2 100.00
rv_dm_rom_read_access 1.170s 78.183us 2 2 100.00
csr_hw_reset 5 5 100.00
rv_dm_csr_hw_reset 2.790s 260.194us 5 5 100.00
csr_rw 20 20 100.00
rv_dm_csr_rw 3.350s 244.194us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_dm_csr_bit_bash 69.630s 6826.793us 5 5 100.00
csr_aliasing 5 5 100.00
rv_dm_csr_aliasing 75.640s 25887.728us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rv_dm_csr_mem_rw_with_rand_reset 3.930s 456.176us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_dm_csr_aliasing 75.640s 25887.728us 5 5 100.00
rv_dm_csr_rw 3.350s 244.194us 20 20 100.00
mem_walk 5 5 100.00
rv_dm_mem_walk 1.310s 132.432us 5 5 100.00
mem_partial_access 5 5 100.00
rv_dm_mem_partial_access 1.140s 161.754us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 2 2 100.00
rv_dm_smoke 2.720s 1917.126us 2 2 100.00
jtag_dtm_hard_reset 2 2 100.00
rv_dm_jtag_dtm_hard_reset 1.470s 434.264us 2 2 100.00
jtag_dtm_idle_hint 2 2 100.00
rv_dm_jtag_dtm_idle_hint 2.260s 662.555us 2 2 100.00
jtag_dmi_failed_op 2 2 100.00
rv_dm_dmi_failed_op 0.990s 412.182us 2 2 100.00
jtag_dmi_dm_inactive 2 2 100.00
rv_dm_jtag_dmi_dm_inactive 1.530s 944.786us 2 2 100.00
sba 0 40 0.00
rv_dm_sba_tl_access 836.400s 300000.000us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 832.690s 300000.000us 0 20 0.00
bad_sba 0 20 0.00
rv_dm_bad_sba_tl_access 760.260s 300000.000us 0 20 0.00
sba_autoincrement 0 20 0.00
rv_dm_autoincr_sba_tl_access 674.560s 300000.000us 0 20 0.00
jtag_dmi_debug_disabled 0 2 0.00
rv_dm_jtag_dmi_debug_disabled 0.990s 183.395us 0 2 0.00
sba_debug_disabled 2 2 100.00
rv_dm_sba_debug_disabled 2.320s 1143.887us 2 2 100.00
ndmreset_req 2 2 100.00
rv_dm_ndmreset_req 1.690s 807.182us 2 2 100.00
hart_unavail 0 5 0.00
rv_dm_hart_unavail 1.640s 283.005us 0 5 0.00
tap_ctrl_transitions 11 11 100.00
rv_dm_tap_fsm 12.680s 7919.215us 1 1 100.00
rv_dm_tap_fsm_rand_reset 67.090s 14996.660us 10 10 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 1.090s 159.230us 1 1 100.00
stress_all 10 50 20.00
rv_dm_stress_all 7402.970s 10000000.000us 10 50 20.00
alert_test 50 50 100.00
rv_dm_alert_test 1.690s 182.740us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_dm_tl_errors 7.720s 402.369us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_dm_tl_errors 7.720s 402.369us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_dm_csr_aliasing 75.640s 25887.728us 5 5 100.00
rv_dm_csr_hw_reset 2.790s 260.194us 5 5 100.00
rv_dm_csr_rw 3.350s 244.194us 20 20 100.00
rv_dm_same_csr_outstanding 9.230s 2118.293us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_dm_csr_aliasing 75.640s 25887.728us 5 5 100.00
rv_dm_csr_hw_reset 2.790s 260.194us 5 5 100.00
rv_dm_csr_rw 3.350s 244.194us 20 20 100.00
rv_dm_same_csr_outstanding 9.230s 2118.293us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_dm_sec_cm 3.210s 735.129us 5 5 100.00
rv_dm_tl_intg_err 23.860s 9027.715us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
rv_dm_tl_intg_err 23.860s 9027.715us 20 20 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 3 4 75.00
rv_dm_sba_debug_disabled 2.320s 1143.887us 2 2 100.00
rv_dm_debug_disabled 0.840s 73.784us 1 2 50.00
sec_cm_lc_dft_en_intersig_mubi 3 4 75.00
rv_dm_sba_debug_disabled 2.320s 1143.887us 2 2 100.00
rv_dm_debug_disabled 0.840s 73.784us 1 2 50.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 2 2 100.00
rv_dm_smoke 2.720s 1917.126us 2 2 100.00
sec_cm_dm_en_ctrl_lc_gated 9 10 90.00
rv_dm_buffered_enable 2.860s 572.426us 9 10 90.00
sec_cm_sba_tl_lc_gate_fsm_sparse 4 4 100.00
rv_dm_sparse_lc_gate_fsm 1.390s 136.371us 4 4 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 4 4 100.00
rv_dm_sparse_lc_gate_fsm 1.390s 136.371us 4 4 100.00
sec_cm_exec_ctrl_mubi 9 10 90.00
rv_dm_buffered_enable 2.860s 572.426us 9 10 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
rv_dm_stress_all_with_rand_reset 17.990s 1089.039us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 76.400s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
rv_dm_sba_tl_access 36795862643960479013983643276813574465645338076078973091854781208791751299194 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 13185423657093430265413444747701546182092674518128187261546514013465836973413 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 43816432836408352040629968290509171423587143586107390500708578156458842408133 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 1706483505975561384069258186836898715309309387918746786935038173369219266664 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_scanmode 12190394329995005981954482868134026601401895598701094117183406395638417926690 77
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 115453826861877836950217865950527773285767578704381960493635750814227264911584 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 5244158431260872351810197803621586882942837363133247998996225489176273831313 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 99039776668084344614122102737206644137485330629134383641910894846750302997758 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 76199111037310263453602465905264500798174024828109616184225432122089201060219 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 6737905729732603694766774628175694082107075856421576754938028735268491452258 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 105523221752367141536418480837005543815620650016957330937102760554401127739027 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 86827109165319469804606479418786630846844720453835598601355032544397046503304 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 11882402218084494791676768504643627595579953607719381825886070609852885133603 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 83242568869057800418035163666422555168722547020343765603917156259569491613516 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 19867746667644323231607426200215709388965406383265214274262341853415659381788 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 79462547727682616415862165530622095612922320810690005395228861128358068371596 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 9469071071128871652627058556877970581323532766867064612237571424006934482170 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 28578087542701474267046455519468176841989949004433213276717940089279456573697 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 68142171920231885498085745929556978551453979938084054366995029881200581089022 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 10944116851910380747751325884853870061606089231890994463957770788722177027993 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 90989905735296968794728265763271523250115431933621122092692360885364843449300 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 13614137242839843026345140662560914321668554048800396047383269423305470262393 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 90272215203524932533370487538120038548523486047129435171508429237942534532323 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 44147512930330365456711751469254416777519599614078531012524371468614968392380 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 35364308865335610577365878304175670933894121272810394238611021234682424125744 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 96170077197476020052032251597888442730455111503986210496484898341975073397532 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 36224388947573173550550157197845984881878093297986366329127727214341276945353 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 25203573032523567881797402307611638297021838022070085699876871467153056394110 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 96464829936824948138764771594208547165917538536219811027202135087410044536469 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 102638516716030116344717684998060563280955549378052605397134280043826419510775 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 96374627084400391496027871715037884650443175096760987560953769827889367884969 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 431257816979109599602011364935870231273584967128312703433450975693570097251 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 71780047748412304118266281181545292413248093952322829804409273246451689622376 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 35788991913638837813009577609389239855275857435840674377625650460204834431373 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 113007970415567472147373466352313931578758228350203104315471775738371601870637 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 35711122335872552024693506609227587982723242405165772526621270459358941026988 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 71353190647704278861583027942427711299937190548210451447515779048096741810879 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 102977554539855444692541634419460269866786595071024543098037862821732934312404 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 18780014222000171639401675912702867908596469940232385812456780096287724618327 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 43345091531944711628761482544493953441428611526060502639337390546819346790190 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 29786653616795476147116014057989910099419637694618790639068343365497909617793 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 91800460535007096007151200454739475038028764502432003233997919002952828909381 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 47345476964693678175400689959560503679750707453789115525634822564138016244239 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 7511313563173056906301944638078348203811204266337561224042442880052545399949 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 2538042805236134065455889925625709710511514110955924532042432603166726162093 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 43716235933809339998150795475588267922344704695744061151842080842179116381573 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 9395237152530812590343386620590208744562924795687968187393706066220561345556 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 74805069033023355912128110032619039869954592961528949045930685565857081707141 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 79607490455676835183597034483083528398119452417155332077126147499449233660657 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 102402773002683292990069869416760878940572772226920366724020210467203099210558 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 13668361842942535965915473861911883112303994826228151120495424182186784014325 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 113562051158245851773222292768243013257315260830719792551354326409229135679227 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 98120985798370334574683372902932401432372655494217216477314455269610599621839 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 103165390882911492180790406271497042099493246801636424767252471408989523249842 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 109899193606189291407308819260095317961550154742819281866468987055535329604034 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 84603912754945066013837097197737715404546572055093295719131463199892146846216 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 113013602580107949650313990102311704080976320279710581125309276241949026084848 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 96746215679067243604941114866962564109169648006278681774806971376033508432909 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 26933329818599466903393101943234823025783677782142025685730027939028112023787 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 63177273505528172237967363844388826709695123678890919697681287755260568691666 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 23570562914459061689051485337759348923847651002294196722307944425739337557628 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 17741049660148547576966665647316207461027436768940760495560175903442500370154 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 72571160277172675026005169109535286376558009584877344606883509296328867208804 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 63969440130238495278942223335423042893901907255954478008437983428092220371834 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 71093904512023316017645880833834013256904791845380982630673164968455884280738 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 81067311613477745458302652087890799150702735231875129051303867836037327188990 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 59527787354517242019465271799192420568760919910957391403568705070197607092938 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 47139678796129502161832642916052936049557845600829214688601657697434335994674 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 104409990410877423652396765041523845714818469023781732902003384022539750905846 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 2052092280309149868105543602185318785074085323693540770240025704712980124539 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 103831321465317063220897051393107576684309926519181752250749908725475410407620 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 12813218652050719668322893019509336117364799169891630923779988768118681408497 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 22834929523315702162693746066357161115427460741520498670204581866524398063504 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 94717802728965393840240587991657300220657264296860820760139186761066059652575 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 59273188449616319201454294947232429634735403032392034954379761488408999217237 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 55465334067062963863675681878199571708797709107797747080331198233120729797592 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 42683659149614648669067134932952704572374814373375601188947100771878451615063 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_sba_tl_access 81947077567775827700471317161366667366296578969669212618561384347035580662366 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_delayed_resp_sba_tl_access 103281910771524330564977853893902196058435634339814116930541145699982246448866 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 64818937218797270964545041255075058074343955708831349473272449007139491758938 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 23270151484668765741374661426823304064322184750162536801378133255297258656063 86
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 59444465427346515278250363049588880265177767914097474173592548691251524475131 83
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == *'b* (* [*] vs * [*])
rv_dm_mem_tl_access_resuming 74380151755470362310365799176675674261754210236323193852595765306780301448602 77
UVM_INFO @ 112476590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_mem_tl_access_resuming 28482912302254720285479922596295987903636460087698519205664492933410938851110 77
UVM_INFO @ 479736857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 21706961403969340216693649428243766945749667006749753122369434407734225071326 78
UVM_INFO @ 117725328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 49150066586832912790099999353695100835009711050422917757302129912009518168804 103
UVM_INFO @ 1089039375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 69219215671862992599320914968953482921246508115988959264472106877485201420045 81
UVM_INFO @ 134648263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 81463675896042598756315494901869578504912172097389194831528254894645189162785 82
UVM_INFO @ 5754339762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 97262735030132952330154409204750668258611949311851160586106317021340829624324 78
UVM_INFO @ 94495522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 100010820622779476815959256818614582110141448723346976322402984816970570340224 82
UVM_INFO @ 569198126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 37912052511281150296603955160809645697508440004602581610592111843400950028302 78
UVM_INFO @ 115362616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 58513888881215758825736137754276332872353548663218630500667255602036979515211 81
UVM_INFO @ 2234454862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 100744181398581711800404686012161828978751906598440061425418234596285622956952 79
UVM_INFO @ 1141205806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 48387191276077257251571719306451980125603518804344044640596849271808276912950 78
UVM_INFO @ 114306476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 62235735560357103859805748713144940830105480635502613587075848969373322485811 78
UVM_INFO @ 108200950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 95166184214376662874379701346189508189015523464034591008812648504581912398845 84
UVM_INFO @ 10768793525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 54463696582262478124108470684561931122717539864732518820764017159535441664422 79
UVM_INFO @ 1363845731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 84408730900861203368158585770279894730263021659030290564106982694422804533949 79
UVM_INFO @ 1299307483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 71652440323739252334963971145142049654220437219306349742903922583887328650870 80
UVM_INFO @ 1052352672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 115246594748165830676533522606195560228266286336860752819138543882199837132319 80
UVM_INFO @ 742910023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 9106202477290999960657316736308124984287524084129283046203574037465475517652 81
UVM_INFO @ 1402549932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 7956261964449765514602995060346623812865345040769563029864213101489201999133 80
UVM_INFO @ 1328388860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [*] vs * [*])
rv_dm_hart_unavail 59108218966780755991709267450073490384605870610975185275712616610444725761894 77
UVM_INFO @ 48860925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 12613282349528943493066775181724512719647962993150453955463274093875116125629 79
UVM_INFO @ 644881076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 102831854301226209566685599780572201723991145761443481429613075807436671547619 77
UVM_INFO @ 138037936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 4937671965855985672376685015825443450866913922401499321941213919201392599301 78
UVM_INFO @ 543774356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 54192120465735651500948121236210221079527357406021985233485810082442954712105 77
UVM_INFO @ 76029895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 104231297457376072058974890158247422444623035788138730447374550882980947834912 77
UVM_INFO @ 283005032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 67082127940862130119481916690296468027423309130684082856346704394416270793260 82
UVM_INFO @ 497126031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_hart_unavail 62845728430843175349005374882565020859488679529956119209739641001856572040848 77
UVM_INFO @ 68354041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 70953447187330833916915033638123768016787099320239406174305538819654691669583 78
UVM_INFO @ 133465398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 79256676088429991729287243425563381702417992567050033935833073717516247694258 78
UVM_INFO @ 265782859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 115465876403774729197523570466250481400474452188715925946024004452868482407804 100
UVM_INFO @ 823443493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 50699762512107591532150064844099130970581955619600140118896292317530648748301 78
UVM_INFO @ 452511207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 26485927750884794295272369218159992212512718340342740821807407380765883711352 82
UVM_INFO @ 316845991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 89671337257839134928573514594536310101307211241667464476030151887390370543930 92
UVM_INFO @ 6190290304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 10917613190833487269513654137246758250883879491874948524842511742727147379764 78
UVM_INFO @ 200091658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 60719291055755772635094404332494508802001496820130834304948784797496839255586 101
UVM_INFO @ 7259955283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 37351505393830484792856025768406335248196252669926956136213429770889768122740 79
UVM_INFO @ 1368984923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 4158934896452038160936488096201795984350055819458562826863884293772945783569 78
UVM_INFO @ 108641859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 91944254106892193605803121705499091148064777794149029557852104418960944742151 78
UVM_INFO @ 151014316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 36945009436966249458858709617035916897112342714270337598943477486646093797085 79
UVM_INFO @ 326801061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 12029799515228844089476749053886927905616961324035136495297983008561791329332 82
UVM_INFO @ 6905694305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
rv_dm_jtag_dmi_debug_disabled 44411473024477562626361561497813275211772906856069100302445851615123528099707 77
UVM_INFO @ 183394982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 102011797497452848271569980559864995496930630272107419478531917502604066352935 81
UVM_INFO @ 334059103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_jtag_dmi_debug_disabled 35870879459503205364606168637379240094614404376394196851159709860838933868112 77
UVM_INFO @ 250358466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 12437124351647908478251654125317821585340072876823759402675871483940750674975 78
UVM_INFO @ 197393067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 76684533081759200766563726677016710900317105079459874958448927682949737429299 102
UVM_INFO @ 2347254053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 105222353843375315311543611485566370387013300187069142511457246374108609481276 82
UVM_INFO @ 276685510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 27189689461604606129648695010939534645352097925698776045937975165130465094900 79
UVM_INFO @ 3845307371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 50255262927665219518451343446668834943421315860654991242650430525277267209115 78
UVM_INFO @ 262961649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 69399493748930438391025434125407236788480470535863417604185770523412472671117 78
UVM_INFO @ 361274191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 90486444703113802108507930294724987352657048388854425237855570281206302774464 92
UVM_INFO @ 10215653239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 16311095806433139033200324791342415881087169640360802661380933197248271716495 78
UVM_INFO @ 136920887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 58760343510544081673577102447813838386367436096703391896294499926011211759892 78
UVM_INFO @ 117435401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
rv_dm_debug_disabled 89860588404139809430438306181841026135056654402301676832414553377434740496993 79
UVM_INFO @ 60293461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)
rv_dm_stress_all_with_rand_reset 97872273871979003175098961046363964242519835281563875944827348692795400441453 87
UVM_INFO @ 994112215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
rv_dm_stress_all 29766492457191390104529189543239223287765173978336683253694951144068995069300 None
rv_dm_stress_all 16479381915045768297758430676928451255475030919068173093196192924264448317557 None
rv_dm_stress_all 60935008269348916901888939953017898058457992547747954598353485834843189639701 None
rv_dm_stress_all 10472190574721731044876217662712501016111198583505053577799919491483420924401 None
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])
rv_dm_buffered_enable 53460186916733536032579972472609400774980145040216827054807098468051822081913 87
UVM_INFO @ 221033245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---