| V1 |
|
100.00% |
| V2 |
|
92.50% |
| V2S |
|
100.00% |
| V3 |
|
45.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.370s | 435.662us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.910s | 14.935us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.930s | 18.459us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.860s | 90.602us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.160s | 38.728us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.980s | 146.093us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.930s | 18.459us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.160s | 38.728us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 10.510s | 26325.431us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 4.450s | 3583.617us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1119.570s | 1291019.202us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 1119.570s | 1291019.202us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 10.630s | 5613.707us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.890s | 15.094us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.910s | 14.949us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.920s | 210.056us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.920s | 210.056us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.910s | 14.935us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.930s | 18.459us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.160s | 38.728us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.130s | 127.208us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.910s | 14.935us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.930s | 18.459us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.160s | 38.728us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.130s | 127.208us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.520s | 2868.762us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.980s | 919.910us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.980s | 919.910us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 1.250s | 218.706us | 2 | 10 | 20.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 1.910s | 42.626us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 61.240s | 6699.419us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 25632419071419479084053783101159919096240888158324218646046221254112374740859 | 75 |
UVM_INFO @ 177651542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 105126433323447490676973761632059265858214048802322715691733527592369044682538 | 76 |
UVM_INFO @ 1300950043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 62151461848740652251718673114260985098864058382707436813245777303596459432105 | 75 |
UVM_INFO @ 1587790643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 10163518127419175731883714659868189259852250336922157177437630183787006452963 | 75 |
UVM_INFO @ 75916978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 63183133324065049756429297815145418735700892065346971577227702856826301608930 | 75 |
UVM_INFO @ 148563064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 25598639865272720325510207563692892346486657414791804660837214148194986787610 | 75 |
UVM_INFO @ 218706227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 79521581163104863622221814236579932869633050918478183658947852479817544892078 | 75 |
UVM_INFO @ 437433160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 36619116301803369366183537675543298426288329080435448607904009593371492515585 | 75 |
UVM_INFO @ 620247262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 15900298576920372057686080323513390914962777041232990767540866370354066445282 | 75 |
UVM_INFO @ 792252379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106636033806971652293555723022756176095292334509920380405580258682057979797225 | 75 |
UVM_INFO @ 228460207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 75244980127640642965378251232069725411049622909999340661022384689399906736153 | 75 |
UVM_INFO @ 117681958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 83245363743602126970440434324923485025072897941528851455134802706095586586404 | 76 |
UVM_INFO @ 6073975991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 46132425178254755959591009776111191366228125589039132471062456460879941217679 | 75 |
UVM_INFO @ 77180358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 58887238769868955780493889642490205482324184892579547000883862144234975338874 | 76 |
UVM_INFO @ 97714502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 61653722148159965901929481457748307957198037648692445564085792028636708999856 | 75 |
UVM_INFO @ 130771263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 60766512277968664850883831762177064188752510993968007227216344881810893003014 | 75 |
UVM_INFO @ 189315371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 86378443762565068009731120595752376967905210857135390678422243679792727292325 | 76 |
UVM_INFO @ 140419844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 59335410865612235466912180118655939193430282159968147659818884582625463236980 | 75 |
UVM_INFO @ 279598336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 27496820251346898805347964021500135551532802851968837949183007294502265957761 | 75 |
UVM_INFO @ 94478156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 10196651324063609538966821028253439667724406913769100760155530110093574787869 | 75 |
UVM_INFO @ 341388587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 76735866012815076486896887452953285365818303419824675585972546430487214815854 | 76 |
UVM_INFO @ 26325430589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 18312334078903812065222867366908792316118962324672789731013476727305116954821 | 75 |
UVM_INFO @ 308295530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 93601061057222263994256673578297534097958688216896486895993457973158393197410 | 75 |
UVM_INFO @ 65356638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 69051997395948235234044307560048921271485082143874842708755566805423508427530 | 75 |
UVM_INFO @ 145205541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 24525061868462358155664415564608667742994711608609705170252301258654209197195 | 75 |
UVM_INFO @ 552183610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 102945736502595181875711302592463970637944066029103421203435790416608252974837 | 75 |
UVM_INFO @ 65905505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 20422669750744852644725637157600057283856765930964288746965009946759792693668 | 75 |
UVM_INFO @ 264042648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64820552413938021420416313724049720225421530335124554656023242178103923656240 | 75 |
UVM_INFO @ 104359891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 13634264182034748469554612299521443703854540272872667422799730673099812348300 | 75 |
UVM_INFO @ 154280797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 72769665301488451334574860017450046217512774217593509143444253463330036306937 | 75 |
UVM_INFO @ 156462083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 65712079625032720232283608395695187164280859307502358012673413074210170941037 | 75 |
UVM_INFO @ 135554793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 56696007497481332555458619892377650151107583471642020876628953546026420448390 | 75 |
UVM_INFO @ 179225728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 115156897400257408648078657942487679066480023194142821121970209307550538908470 | 75 |
UVM_INFO @ 48481692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | ||||
| rv_timer_max | 65080720822546851940760833612886784975036927616433723092297256913510062210638 | 75 |
UVM_INFO @ 42626081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 55321333853924902910034136591835072796769356632819414539850732896749651293830 | 75 |
UVM_INFO @ 44173531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 90344606349132693371059268892876329230765759811828230002444822930360696034344 | 164 |
UVM_INFO @ 1122534479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 85210951760035210406535406627128734132348602872505590693516415027368115253158 | 392 |
UVM_INFO @ 25926541996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 14539741750835786152632654371612562433556313555045441626912343866358317993815 | 143 |
UVM_INFO @ 520650194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 24282424081301720062266553263835692186244070221341511551057292942359837403539 | 79 |
UVM_INFO @ 8683194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 20175014387109556625753673714100643708445709814343914662175955734719456143918 | 187 |
UVM_INFO @ 1782405839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|