Simulation Results: spi_host

 
10/04/2026 17:12:19 DVSim: v1.29.0 sha: 85f0913 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.82 %
  • code
  • 95.06 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 97.00 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 152.000s 35686.227us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 3.000s 20.541us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 3.000s 50.972us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 393.292us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 3.000s 27.071us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 3.000s 78.469us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 3.000s 50.972us 20 20 100.00
spi_host_csr_aliasing 3.000s 27.071us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 13.770us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 86.721us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 3.000s 54.457us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 38.000s 1080.077us 50 50 100.00
spi_host_error_cmd 2.000s 15.169us 50 50 100.00
spi_host_event 819.000s 29935.962us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 8.000s 889.710us 50 50 100.00
speed 50 50 100.00
spi_host_speed 8.000s 889.710us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 8.000s 889.710us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 260.000s 11381.529us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 92.665us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 8.000s 889.710us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 8.000s 889.710us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 152.000s 35686.227us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 152.000s 35686.227us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 95.000s 9609.712us 50 50 100.00
spien 50 50 100.00
spi_host_spien 267.000s 7655.701us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 256.000s 31085.677us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 16.000s 1629.618us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 38.000s 1080.077us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 4.000s 16.479us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 17.317us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 44.671us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 44.671us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 3.000s 20.541us 5 5 100.00
spi_host_csr_rw 3.000s 50.972us 20 20 100.00
spi_host_csr_aliasing 3.000s 27.071us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 20.039us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 3.000s 20.541us 5 5 100.00
spi_host_csr_rw 3.000s 50.972us 20 20 100.00
spi_host_csr_aliasing 3.000s 27.071us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 20.039us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 2.000s 291.073us 20 20 100.00
spi_host_sec_cm 2.000s 235.970us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 291.073us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 500.000s 38726.153us 10 10 100.00