Simulation Results: ac_range_check

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.95%
V2
95.85%
V2S
100.00%
V3
100.00%
unmapped
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 62.000s 2762.633us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 102.000s 28197.781us 19 20 95.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 137.710us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 4.000s 160.865us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 40.000s 6553.195us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 37.000s 8856.777us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 92.205us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 4.000s 160.865us 20 20 100.00
ac_range_check_csr_aliasing 37.000s 8856.777us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 64.768us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 44.000s 16681.857us 1 1 100.00
stress_all 40 50 80.00
ac_range_check_stress_all 340.000s 11022.554us 40 50 80.00
alert_test 50 50 100.00
ac_range_check_alert_test 2.000s 47.132us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 13.503us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 7.000s 137.226us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 7.000s 137.226us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 137.710us 5 5 100.00
ac_range_check_csr_rw 4.000s 160.865us 20 20 100.00
ac_range_check_csr_aliasing 37.000s 8856.777us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 343.110us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 137.710us 5 5 100.00
ac_range_check_csr_rw 4.000s 160.865us 20 20 100.00
ac_range_check_csr_aliasing 37.000s 8856.777us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 343.110us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 2376.178us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 2376.178us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 2376.178us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 29.000s 2376.178us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 146.000s 8337.329us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 41.152us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 1703.618us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 463.000s 3289.381us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 19 20 95.00
ac_range_check_smoke_high_threshold 64.000s 1301.770us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_stress_all 90579721126318457969436381582253680324529056570365660190548641880506194289451 9470
UVM_ERROR @ 3720794778 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3720794778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 50956808121466150935816732013775548679558282963133924877266896845364611488186 18764
UVM_ERROR @ 3970717105 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3970717105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 18919299000252192582803497325084699547805504705918007053390757404923665310293 4138
UVM_ERROR @ 4752135755 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 4752135755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 79388467292653347060897016109995159484652913987593411135261878564000858731551 4127
UVM_ERROR @ 11933690270 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 11933690270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 86647614647933870132719729075222705897504908808698473290191828440076047703817 4253
UVM_ERROR @ 2749336429 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2749336429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 111592861848611974917504916992247304430513579519431729022813846233206620341237 13515
UVM_ERROR @ 4607630033 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 4607630033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 21959154285615138419800100255128047735099846693480259888712782431960179893854 13385
UVM_ERROR @ 8626026109 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 8626026109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 64804567058972771361769265349864399100151436671142022449356417979605504066462 17720
UVM_ERROR @ 5705684169 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 5705684169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 18653379512971554867013010560863630799775890085837894298322267895174583893489 8474
UVM_ERROR @ 3700523784 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3700523784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 48541901147700587954691549856990990102203898284745403721996450206899133628364 4443
UVM_ERROR @ 17145644459 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 17145644459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 44304169313090070660696247506116328224577552167543497320239284171362129272124 8786
UVM_ERROR @ 8905518390 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 8905518390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:413) scoreboard [scoreboard] No matching transaction found, it can be because all the TL accesses have been filtered. Please check your DUT configuration and your sequence.
ac_range_check_smoke_high_threshold 104759242002752302740719286885679970362694939609314147863844941571886752126189 3522
UVM_ERROR @ 2046860304 ps: (ac_range_check_scoreboard.sv:413) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] No matching transaction found, it can be because all the TL accesses have been filtered. Please check your DUT configuration and your sequence.
UVM_INFO @ 2046860304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---