Simulation Results: aes/masked

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.48 %
  • code
  • 98.15 %
  • assert
  • 98.43 %
  • func
  • 95.87 %
  • block
  • 98.23 %
  • line
  • 99.42 %
  • branch
  • 95.06 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.71%
V2S
96.98%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 35.000s 71.022us 1 1 100.00
smoke 50 50 100.00
aes_smoke 6.000s 229.276us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 75.048us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 69.256us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 8.000s 1025.794us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 106.797us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 159.075us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 69.256us 20 20 100.00
aes_csr_aliasing 3.000s 106.797us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 6.000s 229.276us 50 50 100.00
aes_config_error 10.000s 874.808us 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
key_length 150 150 100.00
aes_smoke 6.000s 229.276us 50 50 100.00
aes_config_error 10.000s 874.808us 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
back2back 100 100 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
aes_b2b 81.000s 1017.670us 50 50 100.00
backpressure 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 6.000s 229.276us 50 50 100.00
aes_config_error 10.000s 874.808us 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
aes_alert_reset 72.000s 5179.932us 50 50 100.00
failure_test 149 150 99.33
aes_man_cfg_err 6.000s 208.282us 49 50 98.00
aes_config_error 10.000s 874.808us 50 50 100.00
aes_alert_reset 72.000s 5179.932us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 9.000s 164.283us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 148.000s 4981.643us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 37.000s 617.490us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 72.000s 5179.932us 50 50 100.00
stress 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
sideload 100 100 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
aes_sideload 23.000s 1488.032us 50 50 100.00
deinitialization 49 50 98.00
aes_deinit 1090.000s 200000.000us 49 50 98.00
stress_all 10 10 100.00
aes_stress_all 145.000s 6093.477us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 13.000s 545.185us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 4.000s 168.951us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 200.556us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 200.556us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 75.048us 5 5 100.00
aes_csr_rw 2.000s 69.256us 20 20 100.00
aes_csr_aliasing 3.000s 106.797us 5 5 100.00
aes_same_csr_outstanding 3.000s 77.273us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 75.048us 5 5 100.00
aes_csr_rw 2.000s 69.256us 20 20 100.00
aes_csr_aliasing 3.000s 106.797us 5 5 100.00
aes_same_csr_outstanding 3.000s 77.273us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 51.000s 4903.133us 50 50 100.00
fault_inject 659 700 94.14
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 574.291us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 23.000s 1854.342us 5 5 100.00
aes_tl_intg_err 4.000s 466.039us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 466.039us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 72.000s 5179.932us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
sec_cm_main_config_sparse 218 220 99.09
aes_smoke 6.000s 229.276us 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
aes_alert_reset 72.000s 5179.932us 50 50 100.00
aes_core_fi 43.000s 10044.444us 68 70 97.14
sec_cm_gcm_config_sparse 268 270 99.26
aes_gcm_save_restore 13.000s 545.185us 100 100 100.00
aes_config_error 10.000s 874.808us 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
aes_core_fi 43.000s 10044.444us 68 70 97.14
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 436.670us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 7.000s 253.109us 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
aes_sideload 23.000s 1488.032us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 7.000s 253.109us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 7.000s 253.109us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 7.000s 253.109us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 7.000s 253.109us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 7.000s 253.109us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 70.000s 2616.125us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 159.000s 10006.273us 49 50 98.00
sec_cm_main_fsm_redun 709 750 94.53
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
aes_ctr_fi 5.000s 115.717us 50 50 100.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 159.000s 10006.273us 49 50 98.00
sec_cm_cipher_fsm_redun 659 700 94.14
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
sec_cm_cipher_ctr_redun 332 350 94.86
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 159.000s 10006.273us 49 50 98.00
sec_cm_ctr_fsm_redun 377 400 94.25
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_ctr_fi 5.000s 115.717us 50 50 100.00
sec_cm_ghash_fsm_sparse 49 50 98.00
aes_fi 159.000s 10006.273us 49 50 98.00
sec_cm_ctrl_sparse 709 750 94.53
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
aes_ctr_fi 5.000s 115.717us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 72.000s 5179.932us 50 50 100.00
sec_cm_main_fsm_local_esc 709 750 94.53
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
aes_ctr_fi 5.000s 115.717us 50 50 100.00
sec_cm_cipher_fsm_local_esc 709 750 94.53
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
aes_ctr_fi 5.000s 115.717us 50 50 100.00
sec_cm_ctr_fsm_local_esc 377 400 94.25
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_ctr_fi 5.000s 115.717us 50 50 100.00
sec_cm_ghash_fsm_local_esc 139 140 99.29
aes_fi 159.000s 10006.273us 49 50 98.00
aes_ghash_fi 4.000s 139.776us 90 90 100.00
sec_cm_data_reg_local_esc 659 700 94.14
aes_fi 159.000s 10006.273us 49 50 98.00
aes_control_fi 59.000s 10006.785us 278 300 92.67
aes_cipher_fi 42.000s 10007.603us 332 350 94.86
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 54.000s 1165.040us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 28462581612441757431972697792240623649712829088554406307720023428671416158874 400
UVM_ERROR @ 1165040271 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1165040271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 65568038841440392710030914665864497505762381257616901131729656143902584084718 250
UVM_ERROR @ 562964372 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 562964372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 50348004460666980435476730562493780204332859151411433448648240596648131367118 202
UVM_ERROR @ 404870378 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 404870378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 12971336223267072285301955487147323529595472719030473485846135180200239153265 531
UVM_ERROR @ 944919766 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 944919766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 45076128669361369148510896054255798242980812113413270561781739549434389966867 316
UVM_ERROR @ 484231144 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 484231144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 99403201776920833497270312269760905174959634105503440475388056871464358136065 700
UVM_ERROR @ 326108456 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 326108456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 42423964545832600989878836829796999381603557068518002407593643296401551953776 693
UVM_FATAL @ 930231178 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 930231178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 26384634442159669916240461604174253234752219552398687490578014732124315693627 174
UVM_FATAL @ 42800465 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 42800465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 11334003016901283733154661979675480608497350074035294988337710699554642784784 585
UVM_FATAL @ 4482953419 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 4482953419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 42318412364573300325408929080979343254441421176406456318547567278630395427003 149
UVM_FATAL @ 95916914 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 95916914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
aes_control_fi 18581139712011601359496628183233015694658406328704621227297609019958720827154 None
Job timed out after 1 minutes
aes_control_fi 74319118546231426534899882493679062888916867573330670854858213691208712722726 None
Job timed out after 1 minutes
aes_control_fi 6150252074180739710151929726067632752059404088724658978235691521094624991124 None
Job timed out after 1 minutes
aes_control_fi 76974751046287072546958425558646710766690789640591937612973388012628441026455 None
Job timed out after 1 minutes
aes_cipher_fi 32700067689219992756432859391083217364356249348660717461364510463635925893435 None
Job timed out after 1 minutes
aes_control_fi 29269693272079214894546594285016793196258757403192637018571325918153520005766 None
Job timed out after 1 minutes
aes_control_fi 59905061178101985558092261227151205613711923847101103470951972699980360023302 None
Job timed out after 1 minutes
aes_control_fi 9282759486158354103865038713789734462711676116013349422698364264811461382569 None
Job timed out after 1 minutes
aes_cipher_fi 72975387565091018331779377281727129552451921398580944809444558547070953178171 None
Job timed out after 1 minutes
aes_cipher_fi 103744753143501922243390959846099874206059386277709528662498690862969657979197 None
Job timed out after 1 minutes
aes_control_fi 49141102655788118078743830769767958383327962087086146251247028327710778995291 None
Job timed out after 1 minutes
aes_control_fi 69952232601082487243258874780829618746232104637282951106387313499147804603990 None
Job timed out after 1 minutes
aes_control_fi 44299614067790677971225482296292587156221241722161571506877347243203629854301 None
Job timed out after 1 minutes
aes_cipher_fi 90511610841777781429797450949232518996271004390898529917419718199178965293349 None
Job timed out after 1 minutes
aes_control_fi 40665962093868442993791268041242120802915620470569301848089049391703316728662 None
Job timed out after 1 minutes
aes_control_fi 108074682850886927392166795419490924202426841904236993912868829523222770637320 None
Job timed out after 1 minutes
aes_cipher_fi 78275127865481919457410700704812309654492596546391398128938566583209668482967 None
Job timed out after 1 minutes
aes_control_fi 32603807383655285277769309835957439438500179682818793327679574209083749270241 None
Job timed out after 1 minutes
aes_cipher_fi 46086147417380378595789789055461877392983554335931748330623556331221178880108 None
Job timed out after 1 minutes
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 106158224793142452525201356584131756625746351084895951658408223455920169512350 144
UVM_FATAL @ 10007603151 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007603151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 43954720991632607872895179510757072242798869349436957066257069892003973048559 143
UVM_FATAL @ 10020986185 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10020986185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 17117211204572654760988237665048400921049616525750129811273935948356955036809 147
UVM_FATAL @ 10024318237 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10024318237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 78198721448232573794533127410351820665434958496729061508859267551638431170999 157
UVM_FATAL @ 10014529821 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014529821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 79590133900041182231433968795935917073161515792586385635389858293596330656738 143
UVM_FATAL @ 10015474188 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015474188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104670240476577071889537010961276040130855698245621572902233868633591995646621 152
UVM_FATAL @ 10117338115 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10117338115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23988880424688551454158562207004159466504902177990636288431518069704856648633 161
UVM_FATAL @ 10008086545 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008086545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 86144871444816391992915346545026764696496368314523637948827382697152005238940 145
UVM_FATAL @ 10033142151 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10033142151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23889435625925322957272635429206853036153176421362638394954289663286830280799 149
UVM_FATAL @ 10043332654 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10043332654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29686689404952873818697682039404235584630337289036064240136802072029082352270 151
UVM_FATAL @ 10029174608 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10029174608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 45256481281661286945006922482644928142762647403062961362455059602067095356917 151
UVM_FATAL @ 10011083375 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011083375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
aes_fi 54266393061481695992854927454753168592150201253467616287520090744626140423775 640400
UVM_FATAL @ 10006272890 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x9a0c6f84, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10006272890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_manual_config_err_vseq.sv:71) virtual_sequencer [aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
aes_man_cfg_err 37493861066981822432778241725889168248875897750156137543521725105588356070382 135
UVM_FATAL @ 57978354 ps: (aes_manual_config_err_vseq.sv:71) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
UVM_INFO @ 57978354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 78853560496509730525887245218797823578846661323089688172901397307727525147633 150
UVM_FATAL @ 10044444470 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10044444470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 42901023748105331179890977710531263181348822891134965052684391382138724525018 143
UVM_FATAL @ 10010321200 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010321200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
aes_deinit 70915893730839067770550577322790191253295011246819593493589885374113715005585 173
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 97526378026524228474847289174125695714258155832527637611815575443217137499415 141
UVM_FATAL @ 10033374338 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10033374338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 92483305387811323064985625170918006540193616525706155582729632123753603237068 152
UVM_FATAL @ 10006785068 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006785068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 100532912038926348362835866173747333109593758289916486967580652027925403788423 148
UVM_FATAL @ 10008028915 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008028915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 63856915605636208849425718997471700366444760894138488026524815695012308580452 144
UVM_FATAL @ 10009182962 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009182962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 44909929516268652024260877750422135724914821815723046200813400328707166143071 157
UVM_FATAL @ 10012273551 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10012273551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90901588318805375001016545231341197246139143793940751248775417946765712474286 145
UVM_FATAL @ 10011205341 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011205341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 63165472285889669209083479469031040203640273703254949008076672377796164921674 143
UVM_FATAL @ 10019815635 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10019815635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 57155117875211692371753966843604498614115952289168350073901487477299805008975 156
UVM_FATAL @ 10014760426 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014760426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 51141143526050876305511569325956448161891442046129013568118820597552738267539 148
UVM_FATAL @ 10013525173 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013525173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
aes_cipher_fi 12674962471098136374507867391653847559845935837651231209527627549462247031498 143
UVM_FATAL @ 10236854235 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x827e9884, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10236854235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---