Simulation Results

Simulation Results: csrng

17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.23 %

code
96.23 %

assert
95.85 %

func
90.62 %

block
98.59 %

line
99.57 %

branch
96.46 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		97.14%
V2S		100.00%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	6.000s	271.724us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	3.000s	144.751us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	3.000s	22.281us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	15.000s	501.232us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	9.000s	345.773us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	5.000s	96.810us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	3.000s	22.281us	20	20	100.00
	csrng_csr_aliasing	9.000s	345.773us	5	5	100.00

1428/1470 passed

97.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	61.000s	3578.271us	500	500	100.00
err				500	500	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
cmds				8	50	16.00
	csrng_cmds	266.000s	20035.808us	8	50	16.00
life cycle				8	50	16.00
	csrng_cmds	266.000s	20035.808us	8	50	16.00
stress_all				50	50	100.00
	csrng_stress_all	886.000s	40848.086us	50	50	100.00
intr_test				50	50	100.00
	csrng_intr_test	4.000s	148.733us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	5.000s	75.078us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	13.000s	808.187us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	13.000s	808.187us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	144.751us	5	5	100.00
	csrng_csr_rw	3.000s	22.281us	20	20	100.00
	csrng_csr_aliasing	9.000s	345.773us	5	5	100.00
	csrng_same_csr_outstanding	4.000s	156.624us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	144.751us	5	5	100.00
	csrng_csr_rw	3.000s	22.281us	20	20	100.00
	csrng_csr_aliasing	9.000s	345.773us	5	5	100.00
	csrng_same_csr_outstanding	4.000s	156.624us	20	20	100.00

V2S

1345/1345 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_tl_intg_err	13.000s	448.477us	20	20	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_csr_rw	3.000s	22.281us	20	20	100.00
	csrng_regwen	4.000s	141.319us	50	50	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	61.000s	3578.271us	500	500	100.00
sec_cm_intersig_mubi				50	50	100.00
	csrng_stress_all	886.000s	40848.086us	50	50	100.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	61.000s	3578.271us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
sec_cm_constants_lc_gated				50	50	100.00
	csrng_stress_all	886.000s	40848.086us	50	50	100.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	61.000s	3578.271us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	13.000s	448.477us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00
	csrng_sec_cm	7.000s	457.912us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	24.000s	1917.595us	200	200	100.00
	csrng_err	4.000s	101.918us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	0.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	95358264312408264296849300526572871956110117859024926470629047513355218443485	130	UVM_FATAL @ 92195922 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 194670326525566064875173674503135861923 [0x927424200ac3a6343ff6c67262c09ca3]) UVM_INFO @ 92195922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	62214563486328390048492111294957281219774085897754998734449433932372479793041	130	UVM_FATAL @ 76647412 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 14255681488436375943942505889924821698 [0xab98b5cdb2da8a4bbb5bf86696ab2c2]) UVM_INFO @ 76647412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18188001682677972084902271561721805290746176897650606071022911112023264882472	130	UVM_FATAL @ 28892352 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 65156558748639534443696196952732025099 [0x3104b25ea60afc054d83afebe819410b]) UVM_INFO @ 28892352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48077588098664023109710942516594124659153864625442006825713047236551740073716	130	UVM_FATAL @ 53529838 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 137101111123375180152241681100526365162 [0x6724b6aa0a9e329e7c2549e82caca9ea]) UVM_INFO @ 53529838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	30831325446747412011488231497217007143625269203974892361763829013169861068558	130	UVM_FATAL @ 347598934 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 47120541136899152204453714264227003114 [0x2373160bc5aa613afdba1edea2773aea]) UVM_INFO @ 347598934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110970127237279106956317922436790148617336652692892487543407318415554150336315	130	UVM_FATAL @ 42743328 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 23462825986674423964070930018527047423 [0x11a6c6a259aa722a7a7fdf8abf276eff]) UVM_INFO @ 42743328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	113717829352859939971929285125142821465788346182814224680562779326172261399738	130	UVM_FATAL @ 210673771 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 11564091592772787028245548100853237690 [0x8b329bc30e11c871a951312d77107ba]) UVM_INFO @ 210673771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	44506497514831213998619292873907368502595470052382105852246861305579672356008	130	UVM_FATAL @ 67364004 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 168356385972142167274716014452482338101 [0x7ea842b09a828378bfbd1079a7a96d35]) UVM_INFO @ 67364004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	14126602302374143143309725880968633332651533291609573192614737437572258867968	130	UVM_FATAL @ 330012131 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 124306223763939821656658741531307623399 [0x5d8482033f9977947a55c7c566c343e7]) UVM_INFO @ 330012131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	5478549044939429038145107957997040640948716614910891171314270907410486227804	130	UVM_FATAL @ 41913250 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 22877413612164933491774521646454668572 [0x11360793611b902d113a9d6ce5b3fd1c]) UVM_INFO @ 41913250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41321263707018124646568380863837521011281716364973591706216592793433979188804	130	UVM_FATAL @ 85407451 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 10496043245623124294737585810523909527 [0x7e576e2d0d19acb74066d7aacfd6d97]) UVM_INFO @ 85407451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92791376049298262681503419140752313228601054036541906323992087711457370915500	139	UVM_FATAL @ 25528427 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 13001147683367542713479010555166403286 [0x9c7ee12162c573695fb845ff39f2ad6]) UVM_INFO @ 25528427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96231758259986489843869385773891094998055016577372775283138646833072862901554	130	UVM_FATAL @ 68828413 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 19172029667174960746216728384386699544 [0xe6c660ad9ca9a73deb45b7f03851118]) UVM_INFO @ 68828413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41297283616758857908715314970132480028864968269267107725294491342404952456397	130	UVM_FATAL @ 258936689 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 281947656468785338144323778459147245949 [0xd41d24b81c4c78c7926059edf3e5197d]) UVM_INFO @ 258936689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103355936813056208960851175738792055545069374111672204091567113273519070680148	130	UVM_FATAL @ 123351775 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 156935292578971854041237305855232583495 [0x7610a34f70868e77e2deaa91f8062747]) UVM_INFO @ 123351775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22295939968810690954452856121302157625321517382079855635543348452624623899052	130	UVM_FATAL @ 52404375 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 135243366656034712790648095504798077115 [0x65beecca53a08306d4b3e09ea59c50bb]) UVM_INFO @ 52404375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	98697688232844363130414033708155291462254910032502767337137854498646781884450	130	UVM_FATAL @ 232524265 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 174604626840700847922236423475140977829 [0x835ba0bfc3ebbea47203b78051df64a5]) UVM_INFO @ 232524265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55419417133045115937069266161944123835586007516637254286446128501302001139861	130	UVM_FATAL @ 56295192 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 17298106448832456158895043242038078928 [0xd037e7e96e0b5989ed89bffc1032dd0]) UVM_INFO @ 56295192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105941275229196600605771971130278435314592536987378898589727322138891653276740	130	UVM_FATAL @ 62620838 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 314858241215631399308879977002596527228 [0xecdf7dd2e812ed07cd9ef98038f76c7c]) UVM_INFO @ 62620838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83914686436231213649179822898024963812059968711796092733492318532041236511780	130	UVM_FATAL @ 353550661 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 306970157979245273876780341255103903948 [0xe6f04d4b3083c81b3dd9590371dcf8cc]) UVM_INFO @ 353550661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	112100480512762104388514236046781130132689476152348610352272466637115461550718	130	UVM_FATAL @ 908985202 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 316054557256604504466576745459686062404 [0xedc5e4c22fce126d3312a39eb5703944]) UVM_INFO @ 908985202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	66080171144767899774730336532869985891064472896596100710983314375330661799723	130	UVM_FATAL @ 213955748 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 118839191463663519724907920754860059040 [0x5967988275cbba4d9e746fd8c9d369a0]) UVM_INFO @ 213955748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46654360775453482352425063970614113074471181207234529518526762562131218097250	139	UVM_FATAL @ 29761588 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 295312888994940163826996467205569626673 [0xde2b318ef9c6deb6e49a3781aed5c231]) UVM_INFO @ 29761588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56433079125686823994427916465993353961719924920600205331239093410060588180737	130	UVM_FATAL @ 163884745 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 308441023627022155480342432009874917039 [0xe80b9491b0fb11853b359cdeb8b146af]) UVM_INFO @ 163884745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45035011114020123712923221759285473428943311557597150117309269729181685280026	130	UVM_FATAL @ 34703485 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 140863005727678740975764829215895003438 [0x69f93a635e29f263a0b3d1a9299f212e]) UVM_INFO @ 34703485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	111996637577717131512735765913579943916052571008461555191313079218028900715481	140	UVM_FATAL @ 58205476 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 305391247245394681688360210345143833493 [0xe5c036fbfa2ab2c86c783af329181395]) UVM_INFO @ 58205476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76102885462704901334728420555439469739252805482308304657329865315475573568753	130	UVM_FATAL @ 90572524 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 166645963164216620926606171129321171179 [0x7d5ed855a681fd93a3ccd2c2138128eb]) UVM_INFO @ 90572524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90391609782552776238840305891267476519035967023333753581851463478758940146281	130	UVM_FATAL @ 68741959 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 151109269199601932770753473467937245523 [0x71ae962e359715af12f66aeb0e5cc953]) UVM_INFO @ 68741959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68056351790409226772235826163364483690367753530251351886106225211209313939116	130	UVM_FATAL @ 558344898 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 104935985620359143601609584465728982393 [0x4ef1ef89b5306154ed762a37c0834d79]) UVM_INFO @ 558344898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105071418584155287404874014069990961396585738058498139240863831551805834047247	150	UVM_FATAL @ 441708902 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 2020823355997050765967007382948478790 [0x1853248aba31b0649728c7d91e6ff46]) UVM_INFO @ 441708902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88687978033314836778600692173407652713833113973013852354857961474695595338223	130	UVM_FATAL @ 88195491 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 287222830683763041705753209321991624249 [0xd8151ae369d1aa5fcaca772933d6d639]) UVM_INFO @ 88195491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90091137330453263886001193443956881682371082146751801853463981565277373647979	130	UVM_FATAL @ 46006988 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 232552650298749958783113385076022222504 [0xaef402e39e960674e3b55010edbe9ea8]) UVM_INFO @ 46006988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6838610429462015920232815835494753644585265178514138114052795143184830306799	130	UVM_FATAL @ 348736720 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 94081578417390139684127825390871502239 [0x46c773f1d6e47bd6d950191ed63bdd9f]) UVM_INFO @ 348736720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7157733626784650156104986529565831988434441812729648564208197561731403039115	130	UVM_FATAL @ 99391463 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 266271363991272727421067767194424274725 [0xc851ffd3b8af2baf1023dde4e6e96f25]) UVM_INFO @ 99391463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	111409330917168267186195088895980346469971134105450287916638377617826381337622	130	UVM_FATAL @ 121580031 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 170114791751907074244245398407518460193 [0x7ffaeac9ce693bcc2dd7bd70d5259921]) UVM_INFO @ 121580031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	csrng_stress_all_with_rand_reset	92412447559639711054158688616802358369759270369393928955431622949382280669098	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	16164680184902862637042536328575058479237394815626364699119941953447531743041	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	92670055420771381151109881044793753831461790992486155046731725636266259311099	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	104539779633366033644161740550099186657184417053467327824102581230424997677937	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	50701382105769893448375200903624743646979313913969549324386030388428694728672	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	6647497222587392482902607019623638656301811676882763946669671749206920968459	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	114190213485231006444489106770547374743494158627402207518607970021644657988989	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	115746697912363711596266586201252663598532460711085595678817357279956378363849	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	27083543534701940386612151808550957895019464070825104647036895376287096787342	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	49819522664195058761509914079493474708749662482131998989522740864522786171423	None	Job timed out after 180 minutes
	csrng_cmds	26262967393280763532034203064442239607754116730869214618292032549930086104861	None	Job timed out after 60 minutes
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])
	csrng_cmds	100548033229399664505867584523864858743888082941036770709678524217099365348428	149	UVM_FATAL @ 168448581 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 168448581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	9292190738584341275172270307425907719423766118647015838230187763355426973171	149	UVM_FATAL @ 118477304 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 118477304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55659604866999837623677976315497586754060080478265734936252275382631040315332	139	UVM_FATAL @ 190049446 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 190049446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83800728151275175162038280652959615488917679915015460451691070244283084083507	139	UVM_FATAL @ 32462184 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 32462184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	86175378693680025810001388616469135968846612263322346659522969554007203426647	139	UVM_FATAL @ 227338169 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 227338169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	102041072199103431356689714603743753271676314406056643507928121792823658618693	133	UVM_ERROR @ 62571210 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (55308318 [0x34bf01e] vs 3043512175 [0xb5684f6f]) reg name: csrng_reg_block.genbits UVM_INFO @ 62571210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---