Simulation Results: dma

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.53 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 77.42 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 29.000s 1070.059us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 28.000s 681.948us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 28.000s 796.212us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 24.023us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 15.240us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 13.000s 992.369us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 307.638us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 62.947us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 15.240us 20 20 100.00
dma_csr_aliasing 7.000s 307.638us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 123.000s 7834.287us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 310.000s 26448.692us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 759.000s 53078.320us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 759.000s 53078.320us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 310.000s 26448.692us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 822.000s 136347.900us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 759.000s 53078.320us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 26.000s 249.892us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 167.000s 19245.278us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 108.792us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 34.247us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 494.654us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 494.654us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 24.023us 5 5 100.00
dma_csr_rw 2.000s 15.240us 20 20 100.00
dma_csr_aliasing 7.000s 307.638us 5 5 100.00
dma_same_csr_outstanding 3.000s 118.417us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 24.023us 5 5 100.00
dma_csr_rw 2.000s 15.240us 20 20 100.00
dma_csr_aliasing 7.000s 307.638us 5 5 100.00
dma_same_csr_outstanding 3.000s 118.417us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 53.000s 1011.541us 5 5 100.00
dma_generic_stress 822.000s 136347.900us 5 5 100.00
dma_handshake_stress 759.000s 53078.320us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 21.000s 6814.858us 15 15 100.00
tl_intg_err 25 25 100.00
dma_sec_cm 2.000s 13.171us 5 5 100.00
dma_tl_intg_err 5.000s 407.896us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 162.000s 62864.715us 25 25 100.00
dma_longer_transfer 22.000s 500.269us 5 5 100.00
dma_stress_all_with_rand_reset 19.000s 2792.074us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 61107676925014366553735123574426970094145466550720559022035426134197000316830 106
UVM_ERROR @ 2792073701ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2792073701ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---