Simulation Results: hmac

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.84 %
  • code
  • 98.73 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.540s 586.027us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.110s 18.524us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.260s 116.446us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 11.400s 5111.120us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.630s 593.994us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 763.760s 351931.381us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.260s 116.446us 20 20 100.00
hmac_csr_aliasing 6.630s 593.994us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 80.630s 14863.068us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 96.030s 7720.987us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 266.380s 21831.857us 30 30 100.00
hmac_test_sha384_vectors 574.890s 13350.935us 75 75 100.00
hmac_test_sha512_vectors 510.570s 24975.444us 75 75 100.00
hmac_test_hmac256_vectors 15.580s 1468.294us 50 50 100.00
hmac_test_hmac384_vectors 18.010s 1571.309us 60 60 100.00
hmac_test_hmac512_vectors 20.200s 1663.498us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 47.780s 24577.465us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1501.790s 66408.471us 10 10 100.00
error 10 10 100.00
hmac_error 95.680s 20607.277us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 130.530s 107868.001us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.540s 586.027us 10 10 100.00
hmac_long_msg 80.630s 14863.068us 10 10 100.00
hmac_back_pressure 96.030s 7720.987us 25 25 100.00
hmac_datapath_stress 1501.790s 66408.471us 10 10 100.00
hmac_burst_wr 47.780s 24577.465us 50 50 100.00
hmac_stress_all 1744.830s 12508.099us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.540s 586.027us 10 10 100.00
hmac_long_msg 80.630s 14863.068us 10 10 100.00
hmac_back_pressure 96.030s 7720.987us 25 25 100.00
hmac_datapath_stress 1501.790s 66408.471us 10 10 100.00
hmac_wipe_secret 130.530s 107868.001us 10 10 100.00
hmac_test_sha256_vectors 266.380s 21831.857us 30 30 100.00
hmac_test_sha384_vectors 574.890s 13350.935us 75 75 100.00
hmac_test_sha512_vectors 510.570s 24975.444us 75 75 100.00
hmac_test_hmac256_vectors 15.580s 1468.294us 50 50 100.00
hmac_test_hmac384_vectors 18.010s 1571.309us 60 60 100.00
hmac_test_hmac512_vectors 20.200s 1663.498us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.540s 586.027us 10 10 100.00
hmac_long_msg 80.630s 14863.068us 10 10 100.00
hmac_back_pressure 96.030s 7720.987us 25 25 100.00
hmac_datapath_stress 1501.790s 66408.471us 10 10 100.00
hmac_burst_wr 47.780s 24577.465us 50 50 100.00
hmac_error 95.680s 20607.277us 10 10 100.00
hmac_wipe_secret 130.530s 107868.001us 10 10 100.00
hmac_test_sha256_vectors 266.380s 21831.857us 30 30 100.00
hmac_test_sha384_vectors 574.890s 13350.935us 75 75 100.00
hmac_test_sha512_vectors 510.570s 24975.444us 75 75 100.00
hmac_test_hmac256_vectors 15.580s 1468.294us 50 50 100.00
hmac_test_hmac384_vectors 18.010s 1571.309us 60 60 100.00
hmac_test_hmac512_vectors 20.200s 1663.498us 75 75 100.00
hmac_stress_all 1744.830s 12508.099us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1744.830s 12508.099us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 13.978us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.880s 55.951us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.990s 1750.939us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.990s 1750.939us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.110s 18.524us 5 5 100.00
hmac_csr_rw 1.260s 116.446us 20 20 100.00
hmac_csr_aliasing 6.630s 593.994us 5 5 100.00
hmac_same_csr_outstanding 2.400s 105.994us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.110s 18.524us 5 5 100.00
hmac_csr_rw 1.260s 116.446us 20 20 100.00
hmac_csr_aliasing 6.630s 593.994us 5 5 100.00
hmac_same_csr_outstanding 2.400s 105.994us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 4.330s 295.755us 20 20 100.00
hmac_sec_cm 1.520s 84.505us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.330s 295.755us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.540s 586.027us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.180s 320.638us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 1179.490s 150452.736us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.200s 26.699us 1 1 100.00