Simulation Results: kmac/unmasked

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.51 %
  • code
  • 92.38 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.57%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 65.820s 18532.843us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.540s 53.890us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.440s 21.123us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.690s 1543.370us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.230s 535.690us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.790s 75.484us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.440s 21.123us 20 20 100.00
kmac_csr_aliasing 7.230s 535.690us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.100s 13.748us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.860s 332.230us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3778.470s 630838.771us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 944.120s 101296.245us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1936.620s 1023646.016us 5 5 100.00
kmac_test_vectors_sha3_256 1709.210s 240596.766us 5 5 100.00
kmac_test_vectors_sha3_384 1562.800s 912534.566us 5 5 100.00
kmac_test_vectors_sha3_512 905.130s 189002.154us 5 5 100.00
kmac_test_vectors_shake_128 2160.360s 119651.776us 5 5 100.00
kmac_test_vectors_shake_256 1302.250s 16606.745us 5 5 100.00
kmac_test_vectors_kmac 3.000s 77.171us 5 5 100.00
kmac_test_vectors_kmac_xof 2.840s 165.568us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 415.450s 42491.299us 50 50 100.00
app 50 50 100.00
kmac_app 319.540s 76970.550us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 270.070s 44279.058us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 292.060s 15579.197us 50 50 100.00
error 50 50 100.00
kmac_error 411.140s 20162.756us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 13.770s 32639.187us 49 50 98.00
sideload_invalid 40 50 80.00
kmac_sideload_invalid 92.910s 10035.456us 40 50 80.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 46.920s 4014.255us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 47.880s 8716.161us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 72.350s 38255.285us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 33.770s 2362.436us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2984.090s 110850.309us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.150s 53.479us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.290s 93.656us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.860s 522.656us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.860s 522.656us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.540s 53.890us 5 5 100.00
kmac_csr_rw 1.440s 21.123us 20 20 100.00
kmac_csr_aliasing 7.230s 535.690us 5 5 100.00
kmac_same_csr_outstanding 2.510s 42.267us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.540s 53.890us 5 5 100.00
kmac_csr_rw 1.440s 21.123us 20 20 100.00
kmac_csr_aliasing 7.230s 535.690us 5 5 100.00
kmac_same_csr_outstanding 2.510s 42.267us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.210s 70.045us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.210s 70.045us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.210s 70.045us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.210s 70.045us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.590s 763.319us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.290s 822.459us 20 20 100.00
kmac_sec_cm 82.990s 10343.905us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.290s 822.459us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 33.770s 2362.436us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 65.820s 18532.843us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 415.450s 42491.299us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.210s 70.045us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 82.990s 10343.905us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 82.990s 10343.905us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 82.990s 10343.905us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 65.820s 18532.843us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 33.770s 2362.436us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 82.990s 10343.905us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 256.110s 64913.606us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 65.820s 18532.843us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
kmac_stress_all_with_rand_reset 221.700s 10339.894us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 1862641196246009382093737829247914027208043458324505833811650743266281719275 85
UVM_FATAL @ 10052714769 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x40efe000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10052714769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25)
kmac_sideload_invalid 16290393100750567962405992755713205155674992374215640243570644129914042135377 102
UVM_FATAL @ 10883756414 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x21cbc000, Comparison=CompareOpEq, exp_data=0x1, call_count=25)
UVM_INFO @ 10883756414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 103916811226410846825374889475709489107899241450053345031078928598027823849103 85
UVM_FATAL @ 10154297667 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3638a000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10154297667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 47366006640788161162980686313457309355277796405491979632598283667194327248982 85
UVM_FATAL @ 10262443548 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x66fc6000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10262443548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16)
kmac_sideload_invalid 57880467328800581027012146172180861154236384114544669642897253536372049662766 94
UVM_FATAL @ 10440879749 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xca846000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 10440879749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 12419333342153844313805322599926527978876351273444626501414143619742506450853 93
UVM_FATAL @ 10359252102 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcc39000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10359252102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 9605626255681230945678512985067361647450286125892752296591695868968077318490 83
UVM_FATAL @ 10081302805 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2af1f000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10081302805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 66117763148952411344494886390945189771836720628640452276540889050880639234475 78
UVM_FATAL @ 10012666246 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5dfd2000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10012666246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 90092454984684001952280573054620186112092754394365935401717891427869378477049 79
UVM_FATAL @ 10027129419 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1c7ea000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10027129419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 104436027536531843113315117292511438945499940870660417964111417119021810062688 80
UVM_FATAL @ 10035456190 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5ea13000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10035456190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: *
kmac_key_error 82593773142062814338372492618385699383107599605288139280695733991218174218527 77
UVM_ERROR @ 129256480 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 129256480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---