Simulation Results: lc_ctrl/volatile_unlock_enabled

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.78 %
  • code
  • 89.32 %
  • assert
  • 95.99 %
  • func
  • 96.04 %
  • line
  • 97.87 %
  • branch
  • 96.85 %
  • cond
  • 82.35 %
  • toggle
  • 91.35 %
  • FSM
  • 78.18 %
Validation stages
V1
100.00%
V2
99.73%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 9.290s 207.217us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.380s 23.391us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.400s 16.736us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.940s 373.838us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.200s 19.858us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.850s 59.708us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.400s 16.736us 20 20 100.00
lc_ctrl_csr_aliasing 1.200s 19.858us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.850s 232.271us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 16.620s 710.800us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.390s 16.403us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 3.650s 192.944us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 15.640s 1499.179us 49 50 98.00
security_escalation 259 260 99.62
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_prog_failure 3.650s 192.944us 50 50 100.00
lc_ctrl_errors 15.640s 1499.179us 49 50 98.00
lc_ctrl_security_escalation 21.630s 650.267us 50 50 100.00
lc_ctrl_jtag_state_failure 80.450s 15196.361us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.840s 619.027us 20 20 100.00
lc_ctrl_jtag_errors 81.400s 5633.963us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_csr_hw_reset 3.340s 149.704us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.850s 92.529us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 39.670s 9237.850us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.970s 2447.370us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.660s 44.604us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.670s 120.806us 10 10 100.00
lc_ctrl_jtag_alert_test 1.730s 269.258us 10 10 100.00
lc_ctrl_jtag_smoke 11.850s 3101.314us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.220s 621.469us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.840s 619.027us 20 20 100.00
lc_ctrl_jtag_errors 81.400s 5633.963us 20 20 100.00
lc_ctrl_jtag_access 26.800s 5538.342us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.950s 1533.024us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 40.480s 10004.506us 9 10 90.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.600s 17.956us 50 50 100.00
stress_all 50 50 100.00
lc_ctrl_stress_all 401.130s 28650.056us 50 50 100.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.910s 29.724us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.620s 122.730us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.620s 122.730us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.380s 23.391us 5 5 100.00
lc_ctrl_csr_rw 1.400s 16.736us 20 20 100.00
lc_ctrl_csr_aliasing 1.200s 19.858us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.280s 47.118us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.380s 23.391us 5 5 100.00
lc_ctrl_csr_rw 1.400s 16.736us 20 20 100.00
lc_ctrl_csr_aliasing 1.200s 19.858us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.280s 47.118us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_tl_intg_err 3.770s 108.619us 20 20 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.770s 108.619us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 16.620s 710.800us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 16.690s 1332.593us 50 50 100.00
lc_ctrl_sec_cm 13.210s 996.283us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 21.630s 650.267us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.850s 232.271us 50 50 100.00
lc_ctrl_jtag_state_post_trans 25.220s 621.469us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.660s 1889.855us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 16.660s 1889.855us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.760s 899.579us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.640s 1482.050us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 16.640s 1482.050us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 50 60.00
lc_ctrl_stress_all_with_rand_reset 115.610s 7962.968us 30 50 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 113964222695805953904689103039687691885454933041666272304749185312638131576780 151
UVM_ERROR @ 2944274661 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2944274661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7639545580580584857886525229388957356589938274694066108552597751677698228527 5348
UVM_ERROR @ 7757758506 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7757758506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81280556672748758029006046544028214365416530151936045716283329825208782889690 2424
UVM_ERROR @ 2040243130 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2040243130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31707741596404458208349081356896361936210277730465074461814537345451023158281 4063
UVM_ERROR @ 2879241537 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2879241537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19387947971522867630124041995281650293487736458406144845565870365923512670820 151
UVM_ERROR @ 147364915 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 147364915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91355838245500901010467195750082393676903843743703654208674718903633181305120 4746
UVM_ERROR @ 4883089145 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4883089145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26170265448272594704800169161696534705611501998268274315735458919683820033708 8825
UVM_ERROR @ 2519270454 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2519270454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32104759277877128444774904900193195803245046532681260719552617025971102425053 2183
UVM_ERROR @ 4218361071 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4218361071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113045854154195636845160571664233104918494870965399160503169312779603417123896 156
UVM_ERROR @ 1653230571 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1653230571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113921395477135492107821627861714105629426450456588545588851413493227119892219 4010
UVM_ERROR @ 15060756531 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15060756531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107484856723859464544139331021829724663073511667756899177178500792442253346253 195
UVM_ERROR @ 377770628 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 377770628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84019951154276581537326827137730091348457235864220245182064108065463198378744 650
UVM_ERROR @ 727445621 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 727445621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91913472589194692513698028077251335840130380914851913549009919401434614901185 198
UVM_ERROR @ 693266907 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 693266907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46372642936670905542287663416083971740930679053616195079580359116864284732611 4582
UVM_ERROR @ 50033597568 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 50033597568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52220037685620433879801908560042355216602666657711828401126799367074051426517 3711
UVM_ERROR @ 4893503442 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4893503442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67481162986405647360776076969601886978736383695048609497433857297942834632733 5293
UVM_ERROR @ 2432390792 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2432390792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 106311246907806215975092815338112334061801067061669154295706143796117093678802 154
UVM_ERROR @ 311628338 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 311628338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25533334355504931072990357231480586259717908529881905767344520725027194118187 806
UVM_ERROR @ 881984112 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 881984112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60093713690383686044703438481567839210230570751431722748124102659139343271077 263
UVM_ERROR @ 118877130 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 118877130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred!
lc_ctrl_jtag_priority 97314212212207066410279299917251998543468958309331856857631214211087055125601 148
UVM_FATAL @ 10004506114 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
UVM_INFO @ 10004506114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
lc_ctrl_stress_all_with_rand_reset 72326027233624491223679179634165539150651816334942402679131360948023400756068 2195
UVM_ERROR @ 1283433808 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
UVM_INFO @ 1283433808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*])
lc_ctrl_errors 100201824403368561071621378720404038165043608460512641469532273240989599917939 2474
UVM_ERROR @ 170973642 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 170973642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---