| V1 |
|
100.00% |
| V2 |
|
97.83% |
| V2S |
|
96.46% |
| V3 |
|
10.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 11.000s | 185.032us | 1 | 1 | 100.00 | |
| single_binary | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| otbn_csr_hw_reset | 6.000s | 24.956us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| otbn_csr_rw | 4.000s | 16.932us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| otbn_csr_bit_bash | 8.000s | 96.093us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| otbn_csr_aliasing | 6.000s | 32.676us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 8.000s | 443.429us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| otbn_csr_rw | 4.000s | 16.932us | 20 | 20 | 100.00 | |
| otbn_csr_aliasing | 6.000s | 32.676us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| otbn_mem_walk | 105.000s | 3679.757us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| otbn_mem_partial_access | 56.000s | 5829.903us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 9 | 10 | 90.00 | |||
| otbn_reset | 60.000s | 205.651us | 9 | 10 | 90.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 58.000s | 347.665us | 1 | 1 | 100.00 | |
| back_to_back | 10 | 10 | 100.00 | |||
| otbn_multi | 219.000s | 855.160us | 10 | 10 | 100.00 | |
| stress_all | 9 | 10 | 90.00 | |||
| otbn_stress_all | 125.000s | 344.147us | 9 | 10 | 90.00 | |
| lc_escalation | 58 | 60 | 96.67 | |||
| otbn_escalate | 28.000s | 66.776us | 58 | 60 | 96.67 | |
| zero_state_err_urnd | 4 | 5 | 80.00 | |||
| otbn_zero_state_err_urnd | 10.000s | 72.681us | 4 | 5 | 80.00 | |
| sw_errs_fatal_chk | 9 | 10 | 90.00 | |||
| otbn_sw_errs_fatal_chk | 29.000s | 77.923us | 9 | 10 | 90.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| otbn_alert_test | 16.000s | 62.915us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| otbn_intr_test | 7.000s | 23.243us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| otbn_tl_errors | 9.000s | 53.366us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| otbn_tl_errors | 9.000s | 53.366us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| otbn_csr_hw_reset | 6.000s | 24.956us | 5 | 5 | 100.00 | |
| otbn_csr_rw | 4.000s | 16.932us | 20 | 20 | 100.00 | |
| otbn_csr_aliasing | 6.000s | 32.676us | 5 | 5 | 100.00 | |
| otbn_same_csr_outstanding | 5.000s | 71.591us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| otbn_csr_hw_reset | 6.000s | 24.956us | 5 | 5 | 100.00 | |
| otbn_csr_rw | 4.000s | 16.932us | 20 | 20 | 100.00 | |
| otbn_csr_aliasing | 6.000s | 32.676us | 5 | 5 | 100.00 | |
| otbn_same_csr_outstanding | 5.000s | 71.591us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 24 | 25 | 96.00 | |||
| otbn_imem_err | 11.000s | 62.713us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 21.000s | 33.735us | 15 | 15 | 100.00 | |
| internal_integrity | 17 | 17 | 100.00 | |||
| otbn_alu_bignum_mod_err | 14.000s | 62.758us | 5 | 5 | 100.00 | |
| otbn_controller_ispr_rdata_err | 11.000s | 75.175us | 5 | 5 | 100.00 | |
| otbn_mac_bignum_acc_err | 14.000s | 34.282us | 5 | 5 | 100.00 | |
| otbn_urnd_err | 7.000s | 19.627us | 2 | 2 | 100.00 | |
| illegal_bus_access | 5 | 5 | 100.00 | |||
| otbn_illegal_mem_acc | 9.000s | 17.721us | 5 | 5 | 100.00 | |
| otbn_mem_gnt_acc_err | 2 | 2 | 100.00 | |||
| otbn_mem_gnt_acc_err | 8.000s | 26.587us | 2 | 2 | 100.00 | |
| otbn_non_sec_partial_wipe | 7 | 10 | 70.00 | |||
| otbn_partial_wipe | 7.000s | 46.633us | 7 | 10 | 70.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| otbn_tl_intg_err | 46.000s | 264.127us | 20 | 20 | 100.00 | |
| passthru_mem_tl_intg_err | 17 | 20 | 85.00 | |||
| otbn_passthru_mem_tl_intg_err | 76.000s | 285.673us | 17 | 20 | 85.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 11.000s | 185.032us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 15 | 15 | 100.00 | |||
| otbn_dmem_err | 21.000s | 33.735us | 15 | 15 | 100.00 | |
| sec_cm_instruction_mem_integrity | 9 | 10 | 90.00 | |||
| otbn_imem_err | 11.000s | 62.713us | 9 | 10 | 90.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| otbn_tl_intg_err | 46.000s | 264.127us | 20 | 20 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 58 | 60 | 96.67 | |||
| otbn_escalate | 28.000s | 66.776us | 58 | 60 | 96.67 | |
| sec_cm_controller_fsm_local_esc | 38 | 40 | 95.00 | |||
| otbn_imem_err | 11.000s | 62.713us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 21.000s | 33.735us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 10.000s | 72.681us | 4 | 5 | 80.00 | |
| otbn_illegal_mem_acc | 9.000s | 17.721us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_controller_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 38 | 40 | 95.00 | |||
| otbn_imem_err | 11.000s | 62.713us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 21.000s | 33.735us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 10.000s | 72.681us | 4 | 5 | 80.00 | |
| otbn_illegal_mem_acc | 9.000s | 17.721us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 58 | 60 | 96.67 | |||
| otbn_escalate | 28.000s | 66.776us | 58 | 60 | 96.67 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 38 | 40 | 95.00 | |||
| otbn_imem_err | 11.000s | 62.713us | 9 | 10 | 90.00 | |
| otbn_dmem_err | 21.000s | 33.735us | 15 | 15 | 100.00 | |
| otbn_zero_state_err_urnd | 10.000s | 72.681us | 4 | 5 | 80.00 | |
| otbn_illegal_mem_acc | 9.000s | 17.721us | 5 | 5 | 100.00 | |
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_data_reg_sw_sca | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_ctrl_redun | 12 | 12 | 100.00 | |||
| otbn_ctrl_redun | 20.000s | 76.024us | 12 | 12 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 5 | 5 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 7.000s | 15.544us | 5 | 5 | 100.00 | |
| sec_cm_rnd_bus_consistency | 5 | 5 | 100.00 | |||
| otbn_rnd_sec_cm | 46.000s | 439.993us | 5 | 5 | 100.00 | |
| sec_cm_rnd_rng_digest | 5 | 5 | 100.00 | |||
| otbn_rnd_sec_cm | 46.000s | 439.993us | 5 | 5 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 9 | 10 | 90.00 | |||
| otbn_rf_base_intg_err | 11.000s | 19.766us | 9 | 10 | 90.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 10 | 10 | 100.00 | |||
| otbn_rf_bignum_intg_err | 19.000s | 94.761us | 10 | 10 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_loop_stack_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| sec_cm_loop_stack_addr_integrity | 4 | 5 | 80.00 | |||
| otbn_stack_addr_integ_chk | 25.000s | 59.359us | 4 | 5 | 80.00 | |
| sec_cm_call_stack_addr_integrity | 4 | 5 | 80.00 | |||
| otbn_stack_addr_integ_chk | 25.000s | 59.359us | 4 | 5 | 80.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 7 | 7 | 100.00 | |||
| otbn_sec_wipe_err | 10.000s | 307.079us | 7 | 7 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_write_mem_integrity | 10 | 10 | 100.00 | |||
| otbn_multi | 219.000s | 855.160us | 10 | 10 | 100.00 | |
| sec_cm_ctrl_flow_count | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_ctrl_flow_sca | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 5 | 5 | 100.00 | |||
| otbn_sw_no_acc | 19.000s | 164.338us | 5 | 5 | 100.00 | |
| sec_cm_key_sideload | 100 | 100 | 100.00 | |||
| otbn_single | 276.000s | 913.089us | 100 | 100 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| otbn_sec_cm | 225.000s | 12366.951us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 10 | 10.00 | |||
| otbn_stress_all_with_rand_reset | 379.000s | 1501.874us | 1 | 10 | 10.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 7.000s | 87.879us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job returned non-zero exit code | ||||
| otbn_reset | 47507158165535550275053373156698454659487617118426577837044835890063255516767 | None |
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 47507158165535550275053373156698454659487617118426577837044835890063255516767 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest
2026/04/18 03:33:10 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
|
|
| otbn_sw_errs_fatal_chk | 80288545674525666941893879014446491025131136810335251654436009593329608520237 | None |
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 80288545674525666941893879014446491025131136810335251654436009593329608520237 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_sw_errs_fatal_chk/latest
2026/04/18 03:33:12 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
|
|
| otbn_stress_all | 115031576158230126699590814177511859641887023160162510387802750399062582993125 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| otbn_imem_err | 97780760937031375859110306588350838989088657715189512988808709346607576193252 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) | ||||
| otbn_stress_all_with_rand_reset | 85874893538831733789174663164883335376162222191420688260507553800981777760205 | 184 |
UVM_FATAL @ 35676058 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 35676058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 114058161049207875220065123859923888089108240286110151306834960175133010335635 | 147 |
UVM_FATAL @ 3261669 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 3261669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 39668434876488359149951039986703328039271343213553888067691816007564837633463 | 247 |
UVM_FATAL @ 905830800 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 905830800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed | ||||
| otbn_partial_wipe | 67965372839696932365731215724041538243384337972684952794901487059715189207965 | 119 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 15005313 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 15005313 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 15005313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_partial_wipe | 75638922315809194317327270542770918812387944301310692344884538641515657347641 | 112 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3551437 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3551437 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3551437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) | ||||
| otbn_stress_all_with_rand_reset | 20566179824401941124418501252213078516106587620992611108033972198261722053927 | 227 |
UVM_FATAL @ 1449666998 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1449666998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| otbn_stress_all_with_rand_reset | 15463678756585165208607546022145914025300185386928621422070819002942224113253 | 253 |
UVM_FATAL @ 445943802 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 445943802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed | ||||
| otbn_zero_state_err_urnd | 105433630284586625540031128648360819242833736554234702914514288217065679868850 | 107 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 5500075 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 5500075 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 5500075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_stack_addr_integ_chk | 23302550341994048361707174311763035133118322849269412745782761255156662867229 | 109 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4255706 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 4255706 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4255706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| otbn_escalate | 20135171983286623919821882592688100657256126557186589675138535661382131394155 | 117 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25451429 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 25451429 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 25451429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| otbn_stress_all_with_rand_reset | 86938661134589539033327712241707131611460959682730936387476797671445168255460 | 250 |
UVM_ERROR @ 2823546592 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2823546592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|
| otbn_stress_all_with_rand_reset | 17377391684750397817879240913213907327304263431768312570446229518522721036895 | 414 |
UVM_ERROR @ 898911770 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 898911770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_stress_all_with_rand_reset | 85458018747733410731631336370112974325609124233040676551665342642643958817339 | 424 |
UVM_ERROR @ 1501873667 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1501873667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_stress_all_with_rand_reset | 62490400501780093864402517009043934813376960915377653347131866683395333668134 | 187 |
UVM_ERROR @ 1086984081 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1086984081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed | ||||
| otbn_partial_wipe | 85618092300656991751076645888512302860026170951239166063496768041802820509012 | 115 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 71396527 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
UVM_ERROR @ 71396527 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 71396527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| otbn_rf_base_intg_err | 32787524367252020639258739397902467343894128928461297404283302327934586078594 | 108 |
UVM_ERROR @ 16171477 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 16171477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. | ||||
| otbn_escalate | 98563350616885206249402379309867078725435778691557549110452452317294373505634 | 107 |
UVM_FATAL @ 62107319 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
UVM_INFO @ 62107319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. | ||||
| otbn_passthru_mem_tl_intg_err | 29357251022970907704810890759155769428395867316157266161216885631675798965510 | 91 |
UVM_FATAL @ 19864204 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 19864204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| otbn_passthru_mem_tl_intg_err | 85405912321587661974174389554484980118069735904285550179801480693820711558267 | 106 |
UVM_FATAL @ 140512889 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 140512889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. | ||||
| otbn_passthru_mem_tl_intg_err | 27134857186717969587235459413350670957721756823188585950008137315100482369023 | 101 |
UVM_FATAL @ 124146071 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 124146071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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