Simulation Results: prim_esc

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.78 %
  • code
  • 92.37 %
  • assert
  • 85.19 %
  • line
  • 94.50 %
  • branch
  • 86.67 %
  • cond
  • 87.80 %
  • toggle
  • 100.00 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
prim_esc_request_test 20 20 100.00
prim_esc_test 0.540s 5.243us 20 20 100.00
prim_ping_req_interrupted_by_esc_req_test 20 20 100.00
prim_esc_test 0.540s 5.243us 20 20 100.00
prim_esc_tx_integrity_errors_test 20 20 100.00
prim_esc_test 0.540s 5.243us 20 20 100.00
prim_esc_reverse_ping_timeout_test 20 20 100.00
prim_esc_test 0.540s 5.243us 20 20 100.00
prim_esc_receiver_counter_fail_test 20 20 100.00
prim_esc_test 0.540s 5.243us 20 20 100.00
prim_esc_handshake_with_rand_reset_test 20 20 100.00
prim_esc_test 0.540s 5.243us 20 20 100.00