Simulation Results: rom_ctrl/32kb

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.55 %
  • code
  • 99.58 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.20%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.880s 211.271us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.140s 300.323us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 8.720s 1055.522us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.650s 172.282us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.250s 538.646us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.030s 1077.257us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 8.720s 1055.522us 20 20 100.00
rom_ctrl_csr_aliasing 5.250s 538.646us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 4.310s 529.050us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.470s 558.759us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.050s 142.020us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 25.340s 583.465us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.950s 536.179us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 7.190s 2093.638us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.370s 219.743us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.370s 219.743us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.140s 300.323us 5 5 100.00
rom_ctrl_csr_rw 8.720s 1055.522us 20 20 100.00
rom_ctrl_csr_aliasing 5.250s 538.646us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.330s 836.980us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.140s 300.323us 5 5 100.00
rom_ctrl_csr_rw 8.720s 1055.522us 20 20 100.00
rom_ctrl_csr_aliasing 5.250s 538.646us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.330s 836.980us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.500s 3156.728us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_tl_intg_err 53.670s 302.478us 20 20 100.00
rom_ctrl_sec_cm 341.040s 1072.255us 5 5 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 341.040s 1072.255us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 341.040s 1072.255us 5 5 100.00
sec_cm_checker_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_checker_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_checker_fsm_local_esc 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_compare_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_compare_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 341.040s 1072.255us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 341.040s 1072.255us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.880s 211.271us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.880s 211.271us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.880s 211.271us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 53.670s 302.478us 20 20 100.00
sec_cm_bus_local_esc 18 22 81.82
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
rom_ctrl_kmac_err_chk 8.950s 536.179us 2 2 100.00
sec_cm_mux_mubi 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_mux_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_ctrl_redun 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 102.380s 2729.271us 16 20 80.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.500s 3156.728us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 341.040s 1072.255us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 589.720s 21117.820us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 107530373060023017272748930512299637037167346494005978783027766373653643033674 80
UVM_ERROR @ 193504764 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 193504764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 41161103281647580994444211747330028439379456826330749430614553450979045573110 96
UVM_ERROR @ 844828525 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 844828525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 112728624377948491560888928955966081160358185101869333168114501295919822220086 89
UVM_ERROR @ 425420097 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 425420097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 78020247828108284314994882297903084603489924010192025082571219693233666742816 96
UVM_ERROR @ 632327335 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 632327335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---