| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.980s | 564.306us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 22.500s | 4979.491us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_rw | 12.010s | 1081.212us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 10.760s | 955.350us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_aliasing | 11.940s | 4126.595us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 13.600s | 309.538us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rom_ctrl_csr_rw | 12.010s | 1081.212us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 11.940s | 4126.595us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_walk | 10.520s | 1112.525us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_partial_access | 8.400s | 287.757us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 10.620s | 737.416us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 45.080s | 2114.150us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 16.800s | 2114.246us | 2 | 2 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rom_ctrl_alert_test | 13.970s | 1019.010us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 16.340s | 323.004us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 16.340s | 323.004us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 22.500s | 4979.491us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 12.010s | 1081.212us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 11.940s | 4126.595us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 14.640s | 1388.498us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 22.500s | 4979.491us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 12.010s | 1081.212us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 11.940s | 4126.595us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 14.640s | 1388.498us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 68.520s | 54056.025us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| rom_ctrl_sec_cm | 607.940s | 2151.453us | 5 | 5 | 100.00 | |
| rom_ctrl_tl_intg_err | 137.150s | 434.860us | 20 | 20 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 607.940s | 2151.453us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 607.940s | 2151.453us | 5 | 5 | 100.00 | |
| sec_cm_checker_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 607.940s | 2151.453us | 5 | 5 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 607.940s | 2151.453us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.980s | 564.306us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.980s | 564.306us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.980s | 564.306us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_intg_err | 137.150s | 434.860us | 20 | 20 | 100.00 | |
| sec_cm_bus_local_esc | 22 | 22 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| rom_ctrl_kmac_err_chk | 16.800s | 2114.246us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_mux_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_redun | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 272.460s | 15744.234us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 68.520s | 54056.025us | 20 | 20 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 607.940s | 2151.453us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 394.410s | 27165.798us | 20 | 20 | 100.00 | |