| V1 |
|
100.00% |
| V2 |
|
92.50% |
| V2S |
|
100.00% |
| V3 |
|
57.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 3.930s | 226.875us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.650s | 18.599us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.730s | 48.625us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.300s | 90.415us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 0.780s | 13.262us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.090s | 114.059us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.730s | 48.625us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.780s | 13.262us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 22.870s | 876.475us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.140s | 1837.708us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 569.940s | 541189.042us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 569.940s | 541189.042us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 10.840s | 8249.124us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.860s | 13.528us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.610s | 14.098us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.230s | 683.114us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.230s | 683.114us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.650s | 18.599us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.730s | 48.625us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.780s | 13.262us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.760s | 169.535us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.650s | 18.599us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.730s | 48.625us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 0.780s | 13.262us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.760s | 169.535us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.210s | 523.779us | 20 | 20 | 100.00 | |
| rv_timer_sec_cm | 0.890s | 4516.765us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.210s | 523.779us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 4 | 10 | 40.00 | |||
| rv_timer_min | 0.770s | 53.849us | 4 | 10 | 40.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 1.240s | 84.042us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 18 | 20 | 90.00 | |||
| rv_timer_stress_all_with_rand_reset | 47.520s | 6855.158us | 18 | 20 | 90.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | ||||
| rv_timer_min | 112419803589993218712268009169784379018916238839582402679425247903358302196051 | 75 |
UVM_FATAL @ 219897361 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xdd53cf04) == 0x1
UVM_INFO @ 219897361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 55932263000107196877573379394200301727874661409634788968063745171336829363763 | 75 |
UVM_FATAL @ 667074401 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8d012904) == 0x1
UVM_INFO @ 667074401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 42105040602042870725342992489372963767522991571503683744834739228815417442654 | 75 |
UVM_FATAL @ 381581439 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3bd77d04) == 0x1
UVM_INFO @ 381581439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 98714248374015530956156585715462536051304076339299614357052659761874456773223 | 77 |
UVM_FATAL @ 230675644 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe01d6d04) == 0x1
UVM_INFO @ 230675644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 82495197498056026829653765057984762471128219742959018195992675374919218096608 | 76 |
UVM_FATAL @ 272621967 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb18ce304) == 0x1
UVM_INFO @ 272621967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 670238072776197925235511218686155988989850738672392097933599381276183252115 | 75 |
UVM_FATAL @ 114657069 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf2af3904) == 0x1
UVM_INFO @ 114657069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 88827943005543451789606805377110942505887562727520580932027040212040824064160 | 77 |
UVM_FATAL @ 53849008 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x53181904) == 0x1
UVM_INFO @ 53849008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88560763483812096352024996550683078317746919214119868270707752919960659359286 | 75 |
UVM_FATAL @ 22619210637 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc9536d04) == 0x1
UVM_INFO @ 22619210637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 102911363647295225699718679185421239220470034686455802714212952301628149296526 | 76 |
UVM_FATAL @ 63855573 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7934a904) == 0x1
UVM_INFO @ 63855573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 107376420510517441316058055296605136107021823592045490670281972176003744433711 | 75 |
UVM_FATAL @ 750523339 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x7925b04) == 0x1
UVM_INFO @ 750523339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 36797250344168367416004775929050830130290806086673127932109501452338408803865 | 76 |
UVM_FATAL @ 208285393 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xee097904) == 0x1
UVM_INFO @ 208285393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80852221618737021618513279626089572463928692089416260925493366834016052170605 | 76 |
UVM_FATAL @ 603519854 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4a8c2304) == 0x1
UVM_INFO @ 603519854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 13877969405464792254950482630768527636996296724078918107957464937366615860020 | 79 |
UVM_FATAL @ 248683057 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x67849704) == 0x1
UVM_INFO @ 248683057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44539432074614631522063463094589487574310226040174109351729817045837607947072 | 76 |
UVM_FATAL @ 775414997 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3b3ed304) == 0x1
UVM_INFO @ 775414997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 56387759676942454534193993204051231588170329124117106068355482462611894862626 | 75 |
UVM_FATAL @ 126355023 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xad73104) == 0x1
UVM_INFO @ 126355023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 5676347164026368995884673483355028113089182880729389575549581151326844322867 | 75 |
UVM_FATAL @ 342910849 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6607c104) == 0x1
UVM_INFO @ 342910849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 5667695718827684851520789010209013532073576362985831155605060711485211227086 | 75 |
UVM_FATAL @ 876475331 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9884f04) == 0x1
UVM_INFO @ 876475331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 111665624436726718043708099254699100973471063643043294362725279598287739495759 | 76 |
UVM_FATAL @ 216394258 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfd32cb04) == 0x1
UVM_INFO @ 216394258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 2746219432401696207516531492391893434902254786853374161227219220786208515992 | 75 |
UVM_FATAL @ 1962688920 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xacecfd04) == 0x1
UVM_INFO @ 1962688920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 14038352589989317356759903994554823297417117466279505172392322301162889459533 | 75 |
UVM_FATAL @ 1573482783 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xcb11ed04) == 0x1
UVM_INFO @ 1573482783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 61081927834581904134594009118232622091000295008045556224216260082410359204993 | 75 |
UVM_FATAL @ 103505163 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc48a6704) == 0x1
UVM_INFO @ 103505163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 115029760228945843160702888111722460561520217241495728391545474539778572176037 | 75 |
UVM_FATAL @ 603985314 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa9504704) == 0x1
UVM_INFO @ 603985314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 46628762819171225953826013342292548317691278804264357005291970910518257252867 | 76 |
UVM_FATAL @ 2112266825 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc13db304) == 0x1
UVM_INFO @ 2112266825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 10261943493564555664379104126898658050585835933278270787086438711228543213563 | 75 |
UVM_FATAL @ 216877930 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x3f4a2504) == 0x1
UVM_INFO @ 216877930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | ||||
| rv_timer_max | 95039836466788851083786380588287844500504645124389296154832395285417169369917 | 76 |
UVM_ERROR @ 192991395 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 192991395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64884997812665756146963949885347955613582295333563424635425189332458047129818 | 75 |
UVM_ERROR @ 206610185 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 206610185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 96641004490473393137631979803050420304781871859257038192470808261062315257823 | 75 |
UVM_ERROR @ 43618021 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43618021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 23543619590363401131687186827360337705968807645986408513078363038762719195945 | 75 |
UVM_ERROR @ 89623390 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 89623390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 55048900420272388326739386004886105897672138772727208721853723225173227531072 | 75 |
UVM_ERROR @ 43744504 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43744504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 14535521632182610810808108215831595512886275188661453925783622846548994391746 | 75 |
UVM_ERROR @ 43862976 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43862976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 66513054002712140669720595668069903321218284548803126730807893150598851940465 | 77 |
UVM_ERROR @ 712372040 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 712372040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 30184719089394312880991347327138444307786427230411384656877767409048689100032 | 75 |
UVM_ERROR @ 185098482 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 185098482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | ||||
| rv_timer_stress_all_with_rand_reset | 17698238892484585229069992719535830981221107073415367154328839779309452498198 | 211 |
UVM_FATAL @ 10290959813 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 10290959813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | ||||
| rv_timer_max | 36593042729003493309862867195617847009273223439356650521324052447586924421246 | 75 |
UVM_ERROR @ 84041873 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 84041873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| rv_timer_stress_all_with_rand_reset | 85018236406859699144658261494711082796475435496225224714652265443182275104492 | 357 |
UVM_ERROR @ 5537101198 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 5537101198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|