Simulation Results: spi_host

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.74%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 118.000s 8360.171us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 39.026us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 17.771us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 55.913us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 48.575us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 22.116us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 17.771us 20 20 100.00
spi_host_csr_aliasing 2.000s 48.575us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 1.000s 16.546us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 43.041us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 22.293us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 33.000s 5420.058us 50 50 100.00
spi_host_error_cmd 2.000s 120.200us 50 50 100.00
spi_host_event 399.000s 15021.025us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 9.000s 426.155us 50 50 100.00
speed 50 50 100.00
spi_host_speed 9.000s 426.155us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 9.000s 426.155us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 21.000s 590.547us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 26.192us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 9.000s 426.155us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 9.000s 426.155us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 118.000s 8360.171us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 118.000s 8360.171us 50 50 100.00
stress_all 49 50 98.00
spi_host_stress_all 1296.000s 1000000.000us 49 50 98.00
spien 50 50 100.00
spi_host_spien 150.000s 16185.247us 50 50 100.00
stall 49 50 98.00
spi_host_status_stall 389.000s 41107.625us 49 50 98.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 35.000s 1646.725us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 33.000s 5420.058us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 15.650us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 48.713us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 233.244us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 233.244us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 39.026us 5 5 100.00
spi_host_csr_rw 2.000s 17.771us 20 20 100.00
spi_host_csr_aliasing 2.000s 48.575us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 111.007us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 39.026us 5 5 100.00
spi_host_csr_rw 2.000s 17.771us 20 20 100.00
spi_host_csr_aliasing 2.000s 48.575us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 111.007us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 71.008us 5 5 100.00
spi_host_tl_intg_err 3.000s 922.415us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 922.415us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 529.000s 100032.728us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_upper_range_clkdiv 35998851561033828153974368779784578306085861136385384859590746569785248872418 159
UVM_FATAL @ 100032727515 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0xf0902d14, Comparison=CompareOpEq, exp_data=0x0, call_count=18
UVM_INFO @ 100032727515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_stress_all 29298162949318435023082611310546991676104735733587196326536269734574045845475 190
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
spi_host_status_stall 52718918913193842620156908790558983822358718958986299750204991486860642394570 1924
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 7480970629 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 7480970629 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=7480971000 ps
UVM_INFO @ 7480970629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---