Simulation Results: sram_ctrl/main

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.90 %
  • code
  • 97.45 %
  • assert
  • 96.46 %
  • func
  • 96.80 %
  • block
  • 96.90 %
  • line
  • 97.37 %
  • branch
  • 96.34 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 9.000s 1387.234us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 29.962us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 17.948us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 244.837us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 35.859us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 7.000s 5891.896us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 17.948us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 35.859us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 324.000s 21082.900us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 109.000s 4591.706us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 38.000s 27059.781us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 323.000s 8311.656us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 177.000s 58793.099us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 96.000s 11462.456us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 101.000s 129945.253us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 64.000s 6528.359us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 9.000s 2819.485us 5 5 100.00
sram_ctrl_partial_access_b2b 435.000s 132021.819us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 8.000s 3455.808us 0 5 0.00
sram_ctrl_throughput_w_partial_write 8.000s 760.099us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 3879.225us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 14.000s 1015.562us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 4.000s 1091.646us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 800.000s 55582.655us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 15.781us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 136.901us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 136.901us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 29.962us 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.948us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 35.859us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 87.130us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 29.962us 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.948us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 35.859us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 87.130us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 56.000s 140707.503us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 1379.818us 20 20 100.00
sram_ctrl_sec_cm 5.000s 621.040us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 621.040us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.000s 1379.818us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 14.000s 1015.562us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 14.000s 1015.562us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 17.948us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 64.000s 6528.359us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 64.000s 6528.359us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 64.000s 6528.359us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 101.000s 129945.253us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 919.639us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 56.000s 140707.503us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 8.000s 953.943us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 1387.234us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 9.000s 1387.234us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 64.000s 6528.359us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 621.040us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 101.000s 129945.253us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 621.040us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 621.040us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 9.000s 1387.234us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 621.040us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 59.000s 2020.178us 5 5 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 68849559897456051010674137938204645960828707446763793890833281405243079146243 102
UVM_FATAL @ 3455808368 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 3455808368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30411910236774303263417699095255617246021858753018955638773141206538275243995 102
UVM_FATAL @ 691374018 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 691374018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 9388915451712980194926896042033223645564764635418257228077604319869105288921 102
UVM_FATAL @ 896273218 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 896273218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 47934491162504733566044186897047518617853340710812422236277049025326427464402 102
UVM_FATAL @ 3879224509 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 3879224509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 112870397577784407713037526282094094966568225171538481625728094638990813648278 102
UVM_FATAL @ 671492851 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 671492851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 43004143725586269422839293629268113317327220059434893554875507737041954668633 102
UVM_FATAL @ 693854699 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 693854699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 101855003635938446702662642969110182324684409519278642811924379884248546061676 102
UVM_FATAL @ 876443100 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 876443100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 57632014448809000234752773838275711990147606385973903637364850790955647314141 102
UVM_FATAL @ 1314117576 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 1314117576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 95027137456306564224259200101240256202137067844792712149753276226416429071174 102
UVM_FATAL @ 658244891 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 658244891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 49737085653488903819845911947048152715049092697895298695795606063170764391449 102
UVM_FATAL @ 692501287 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 692501287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---