Simulation Results: sram_ctrl/ret

 
17/04/2026 17:04:56 DVSim: v1.17.3 sha: 68d4457 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.39 %
  • code
  • 83.93 %
  • assert
  • 96.43 %
  • func
  • 96.80 %
  • block
  • 94.51 %
  • line
  • 95.43 %
  • branch
  • 91.33 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
98.57%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 3.000s 49.267us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 27.000s 13.924us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 27.000s 32.640us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 25.000s 30.258us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 24.000s 48.589us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 20.000s 182.121us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 27.000s 32.640us 20 20 100.00
sram_ctrl_csr_aliasing 24.000s 48.589us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 11.000s 1751.978us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 4.000s 97.730us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 13.000s 769.434us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 276.000s 11076.290us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 8.000s 315.377us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 19.000s 3360.976us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 10.000s 2302.559us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 14.000s 1259.246us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 3.000s 72.966us 5 5 100.00
sram_ctrl_partial_access_b2b 394.000s 90362.824us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 2.000s 25.065us 0 5 0.00
sram_ctrl_throughput_w_partial_write 2.000s 267.343us 5 5 100.00
sram_ctrl_throughput_w_readback 1.000s 45.444us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 12.000s 686.716us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 106.000us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 50.000s 11710.677us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 14.599us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 29.000s 86.463us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 29.000s 86.463us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 27.000s 13.924us 5 5 100.00
sram_ctrl_csr_rw 27.000s 32.640us 20 20 100.00
sram_ctrl_csr_aliasing 24.000s 48.589us 5 5 100.00
sram_ctrl_same_csr_outstanding 23.000s 16.546us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 27.000s 13.924us 5 5 100.00
sram_ctrl_csr_rw 27.000s 32.640us 20 20 100.00
sram_ctrl_csr_aliasing 24.000s 48.589us 5 5 100.00
sram_ctrl_same_csr_outstanding 23.000s 16.546us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 209.651us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 28.000s 159.237us 20 20 100.00
sram_ctrl_sec_cm 5.000s 730.610us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 730.610us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 28.000s 159.237us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 12.000s 686.716us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 12.000s 686.716us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 27.000s 32.640us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 14.000s 1259.246us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 1259.246us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 1259.246us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 10.000s 2302.559us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 82.118us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 209.651us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 104.242us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 49.267us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 49.267us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 14.000s 1259.246us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 730.610us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 10.000s 2302.559us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 730.610us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 730.610us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 3.000s 49.267us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 730.610us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 118.000s 2229.900us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 66047349364669013631705238406675942535646060822416458119121617115205136170444 88
UVM_ERROR @ 96755401 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 96755401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 79886541851468411268284765683679636956379891253028155991772828361640051655542 102
UVM_FATAL @ 23528305 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 23528305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 110321928454092756779339574649467504546827756354700739477822934536198282871915 102
UVM_FATAL @ 45443747 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 45443747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 61358385643942922454793479283655328993862778951517895987325811721047590999776 102
UVM_FATAL @ 25064718 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 25064718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 79417598982216175669068980216564807470426650665198086999611749756028209264758 102
UVM_FATAL @ 136448847 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 136448847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 43718592586282174770572091723704268463439706071357509105704074976710822519689 102
UVM_FATAL @ 94169783 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 94169783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 65793482187353851994745921526864748153875668353245109053943900879393825013404 102
UVM_FATAL @ 70254939 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 70254939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 83224999759914226835109153050385339907377479340936821602085997308548595625401 102
UVM_FATAL @ 48828167 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 48828167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 99868095071193866785385661232412017040326363678854921444598865048413514191516 102
UVM_FATAL @ 92843399 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 92843399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 4417571023516420875194054967467178090695757701618179719154660259535752004077 102
UVM_FATAL @ 29803095 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 29803095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 93744755851403643979035746966197255737649704263049117314831115072324713753411 102
UVM_FATAL @ 90873197 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 90873197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---