Simulation Results: ac_range_check

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
97.89%
V2
97.51%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 64.000s 1670.465us 19 20 95.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 79.000s 2257.845us 19 20 95.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 120.476us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 3.000s 40.988us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 51.000s 6825.880us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 33.000s 2460.028us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 134.007us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 3.000s 40.988us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 2460.028us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 205.713us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 46.000s 7135.918us 1 1 100.00
stress_all 44 50 88.00
ac_range_check_stress_all 273.000s 37920.603us 44 50 88.00
alert_test 50 50 100.00
ac_range_check_alert_test 2.000s 258.547us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 14.133us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 127.605us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 127.605us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 120.476us 5 5 100.00
ac_range_check_csr_rw 3.000s 40.988us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 2460.028us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 137.186us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 120.476us 5 5 100.00
ac_range_check_csr_rw 3.000s 40.988us 20 20 100.00
ac_range_check_csr_aliasing 33.000s 2460.028us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 137.186us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1037.990us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1037.990us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1037.990us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 1037.990us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 149.000s 5446.235us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 33.634us 5 5 100.00
ac_range_check_tl_intg_err 16.000s 3797.734us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 420.000s 5109.578us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 54.000s 2186.846us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke_racl 115264332286139364440278032559125503830304134524223228938885391891493327312766 4206
UVM_ERROR @ 1756433715 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1756433715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 79769493876887729794775237057935669314533921897645899608607914089528697518923 18782
UVM_ERROR @ 44265831623 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 44265831623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 113428801870956297115434289595878932206988791843201337656139153207647818380125 9066
UVM_ERROR @ 5046006511 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 5046006511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 8831332600447940395264669267767721072178162626473249999973319614103784316221 9336
UVM_ERROR @ 14739944164 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 14739944164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 48864216736605976977355601021672946174562195704333565349881179333676412065186 4173
UVM_ERROR @ 11581215292 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 11581215292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 110052333715609283498876079522537118889709226227928062561993277474135965865458 4642
UVM_ERROR @ 1670464920 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1670464920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 85757134466799551116509673664284730479873383977992261202682568026528215405994 13305
UVM_ERROR @ 26100044819 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 26100044819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 8301012625919142060751624710712748057234285820469475809118601556129036480446 8490
UVM_ERROR @ 3187473559 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 3187473559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---