Simulation Results: aes/masked

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 98.13 %
  • assert
  • 98.57 %
  • func
  • 95.72 %
  • block
  • 98.20 %
  • line
  • 99.39 %
  • branch
  • 95.00 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.46%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 163.835us 1 1 100.00
smoke 50 50 100.00
aes_smoke 6.000s 172.440us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 113.743us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 58.884us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 8.000s 1729.405us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 396.973us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 63.897us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 58.884us 20 20 100.00
aes_csr_aliasing 4.000s 396.973us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 6.000s 172.440us 50 50 100.00
aes_config_error 12.000s 2204.203us 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
key_length 150 150 100.00
aes_smoke 6.000s 172.440us 50 50 100.00
aes_config_error 12.000s 2204.203us 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
back2back 100 100 100.00
aes_stress 12.000s 183.789us 50 50 100.00
aes_b2b 30.000s 559.538us 50 50 100.00
backpressure 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 6.000s 172.440us 50 50 100.00
aes_config_error 12.000s 2204.203us 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
aes_alert_reset 16.000s 1115.698us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 4.000s 87.843us 50 50 100.00
aes_config_error 12.000s 2204.203us 50 50 100.00
aes_alert_reset 16.000s 1115.698us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 8.000s 246.936us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 1167.610us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 2560.915us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 16.000s 1115.698us 50 50 100.00
stress 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
sideload 100 100 100.00
aes_stress 12.000s 183.789us 50 50 100.00
aes_sideload 46.000s 1597.921us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 13.000s 523.492us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 171.000s 65533.098us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 15.000s 1951.746us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 66.496us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 284.591us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 284.591us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 113.743us 5 5 100.00
aes_csr_rw 2.000s 58.884us 20 20 100.00
aes_csr_aliasing 4.000s 396.973us 5 5 100.00
aes_same_csr_outstanding 3.000s 79.910us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 113.743us 5 5 100.00
aes_csr_rw 2.000s 58.884us 20 20 100.00
aes_csr_aliasing 4.000s 396.973us 5 5 100.00
aes_same_csr_outstanding 3.000s 79.910us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 15.000s 287.154us 50 50 100.00
fault_inject 679 700 97.00
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 502.665us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 16.000s 1901.748us 5 5 100.00
aes_tl_intg_err 4.000s 387.897us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 387.897us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 16.000s 1115.698us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
sec_cm_main_config_sparse 219 220 99.55
aes_smoke 6.000s 172.440us 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
aes_alert_reset 16.000s 1115.698us 50 50 100.00
aes_core_fi 165.000s 9215.047us 69 70 98.57
sec_cm_gcm_config_sparse 269 270 99.63
aes_gcm_save_restore 15.000s 1951.746us 100 100 100.00
aes_config_error 12.000s 2204.203us 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
aes_core_fi 165.000s 9215.047us 69 70 98.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 131.083us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 78.010us 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 12.000s 183.789us 50 50 100.00
aes_sideload 46.000s 1597.921us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 78.010us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 78.010us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 78.010us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 78.010us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 78.010us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 12.000s 183.789us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 12.000s 647.203us 50 50 100.00
sec_cm_main_fsm_redun 729 750 97.20
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
aes_ctr_fi 4.000s 230.417us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 12.000s 647.203us 50 50 100.00
sec_cm_cipher_fsm_redun 679 700 97.00
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
sec_cm_cipher_ctr_redun 339 350 96.86
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 12.000s 647.203us 50 50 100.00
sec_cm_ctr_fsm_redun 390 400 97.50
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_ctr_fi 4.000s 230.417us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 12.000s 647.203us 50 50 100.00
sec_cm_ctrl_sparse 729 750 97.20
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
aes_ctr_fi 4.000s 230.417us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 16.000s 1115.698us 50 50 100.00
sec_cm_main_fsm_local_esc 729 750 97.20
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
aes_ctr_fi 4.000s 230.417us 50 50 100.00
sec_cm_cipher_fsm_local_esc 729 750 97.20
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
aes_ctr_fi 4.000s 230.417us 50 50 100.00
sec_cm_ctr_fsm_local_esc 390 400 97.50
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_ctr_fi 4.000s 230.417us 50 50 100.00
sec_cm_ghash_fsm_local_esc 140 140 100.00
aes_fi 12.000s 647.203us 50 50 100.00
aes_ghash_fi 7.000s 746.850us 90 90 100.00
sec_cm_data_reg_local_esc 679 700 97.00
aes_fi 12.000s 647.203us 50 50 100.00
aes_control_fi 48.000s 10003.858us 290 300 96.67
aes_cipher_fi 55.000s 10006.360us 339 350 96.86
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 31.000s 1503.276us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 5060440585798049472607124839899048286781895073345658812773913605521388888022 674
UVM_ERROR @ 2178938064 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2178938064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 27793443036384782285556686064760458826659998627538521639371086983266738651351 403
UVM_ERROR @ 2904835721 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2904835721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 64309351744021372440566691913692582635527353370833838927130908216814346249574 702
UVM_ERROR @ 737111645 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 737111645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 81206469300216659063208402483315376501412477153839875023902767444175181739879 281
UVM_FATAL @ 241358807 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 241358807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 44472491427123376745716566875505106329636932874751231627972797573059741551933 739
UVM_FATAL @ 1911005422 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1911005422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 6944571939173269278898072032479046253998536561719757495436047624921785603113 344
UVM_FATAL @ 283169816 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 283169816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 63620674325684330029544275928040241769691089874686704223317980288244801340881 142
UVM_FATAL @ 19792331 ps: (aes_base_vseq.sv:75) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 19792331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 93979608930049953912182848146962736810093373534955008661408857413875582373843 153
UVM_ERROR @ 193660181 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 193660181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 84163343317635236726657360210555763383760553712459362482255623387751685323108 526
UVM_ERROR @ 1503276253 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1503276253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT
aes_stress_all_with_rand_reset 37092534950378058678063411552567931275609820329268719495060746677796252527189 484
UVM_FATAL @ 506072036 ps: (aes_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT
UVM_INFO @ 506072036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 27784237342476641638292547859172857201087830538828271260347579118855434324894 149
UVM_FATAL @ 10020585240 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10020585240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 75920626952280602638347354953921501449709550895521909939493978606081951400185 150
UVM_FATAL @ 10036743328 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10036743328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 13169295676008354320027679067339475070106604509324930966948765797162124691957 146
UVM_FATAL @ 10014920147 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014920147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 92324927320281280522840783813205855342833549403300185707387208888418114521983 145
UVM_FATAL @ 10013499838 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013499838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96985855712272308800080665432810974090154069315945757555495430437580180501040 145
UVM_FATAL @ 10012489127 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10012489127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 71194454378698214160785053754410190752099894171183339175940221176302436396155 148
UVM_FATAL @ 10051177152 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10051177152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 50905921133116809569862602600005125488632824515335341209375515640125907872876 150
UVM_FATAL @ 10015055112 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015055112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 51500886202319126417522456163741933350045336042819701408250423318911591837467 145
UVM_FATAL @ 10006360257 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006360257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
aes_control_fi 2791116274177602294246616001123469043680104686254018081525283036589817315661 None
Job timed out after 1 minutes
aes_control_fi 100167029588313029409124723609818754321877467585962237644333308452039777805517 None
Job timed out after 1 minutes
aes_cipher_fi 72920174211464124475371730116760210111349333741224647241329311124430399249348 None
Job timed out after 1 minutes
aes_cipher_fi 89110381752159598266122629535169061337570426830518425391760553758046968000375 None
Job timed out after 1 minutes
aes_control_fi 111763284237891029369740929768365910762429319678129668674862067076454877713313 None
Job timed out after 1 minutes
aes_control_fi 66392717727887176510077728556900879397726696972563607767532612612121481952910 None
Job timed out after 1 minutes
aes_cipher_fi 100620730893963930157833987033089115976310639606355265083288763372074248634798 None
Job timed out after 1 minutes
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
aes_control_fi 107516259202933461575058320708279673542516334404932401111287947709324321958477 143
UVM_FATAL @ 10006819884 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10006819884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 104569348699136414540523835989392611802423436077069151747816481393408259735334 153
UVM_FATAL @ 10030968473 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10030968473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 44361939019081171518898289990990178688844295046758796789766749789424901966176 146
UVM_FATAL @ 10009033894 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10009033894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 11834456068652566042996910747561621042304321802899345704994751455984088545689 146
UVM_FATAL @ 10494583005 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10494583005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93128819075805532349093973475297956681065128304611590770744957718549984790087 150
UVM_FATAL @ 10017165144 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10017165144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93475254210854470561056281636151645410181407985287561816095935761054812446147 142
UVM_FATAL @ 10003858094 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10003858094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 108781222461100245717384922759843096730205009030083261048165328971934096612363 152
UVM_FATAL @ 10037090567 ps: (aes_core_fi_vseq.sv:70) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10037090567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---