Simulation Results

Simulation Results: csrng

18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.24 %

code
96.26 %

assert
95.85 %

func
90.62 %

block
98.62 %

line
99.61 %

branch
96.55 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.73%
V2S		99.93%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	5.000s	161.733us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	3.000s	20.606us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	3.000s	152.894us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	8.000s	193.515us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	4.000s	181.898us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	4.000s	89.691us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	3.000s	152.894us	20	20	100.00
	csrng_csr_aliasing	4.000s	181.898us	5	5	100.00

1422/1470 passed

96.73 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	49.000s	2252.634us	500	500	100.00
err				500	500	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
cmds				3	50	6.00
	csrng_cmds	112.000s	5853.982us	3	50	6.00
life cycle				3	50	6.00
	csrng_cmds	112.000s	5853.982us	3	50	6.00
stress_all				49	50	98.00
	csrng_stress_all	922.000s	74969.707us	49	50	98.00
intr_test				50	50	100.00
	csrng_intr_test	4.000s	153.016us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	7.000s	117.799us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	10.000s	524.798us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	10.000s	524.798us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	20.606us	5	5	100.00
	csrng_csr_rw	3.000s	152.894us	20	20	100.00
	csrng_csr_aliasing	4.000s	181.898us	5	5	100.00
	csrng_same_csr_outstanding	4.000s	107.233us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	3.000s	20.606us	5	5	100.00
	csrng_csr_rw	3.000s	152.894us	20	20	100.00
	csrng_csr_aliasing	4.000s	181.898us	5	5	100.00
	csrng_same_csr_outstanding	4.000s	107.233us	20	20	100.00

V2S

1344/1345 passed

99.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
	csrng_tl_intg_err	8.000s	405.286us	20	20	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_regwen	3.000s	34.802us	50	50	100.00
	csrng_csr_rw	3.000s	152.894us	20	20	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	49.000s	2252.634us	500	500	100.00
sec_cm_intersig_mubi				49	50	98.00
	csrng_stress_all	922.000s	74969.707us	49	50	98.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	49.000s	2252.634us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
sec_cm_constants_lc_gated				49	50	98.00
	csrng_stress_all	922.000s	74969.707us	49	50	98.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	49.000s	2252.634us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	8.000s	405.286us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00
	csrng_sec_cm	14.000s	1001.444us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	18.000s	1195.048us	200	200	100.00
	csrng_err	8.000s	22.370us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	0.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])
	csrng_cmds	45708739722439397226228316197737246080196836422188498016826159318649259678647	130	UVM_FATAL @ 148702613 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 322064673538891174114230773514338274384 [0xf24b665e8586e28054246048e7fb8c50]) UVM_INFO @ 148702613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	108360175752735745340836635591363935806178747478567518300472196930353774795418	139	UVM_FATAL @ 20949788 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 33278772447919215062093311213483095073 [0x19094228ed32a2f7a1e01a7976d07421]) UVM_INFO @ 20949788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	81912505046495838509948432871071993082626108842446791471350847547503206678358	130	UVM_FATAL @ 206263291 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 49424576409109512307700264513615251956 [0x252ed3c1614d209945882838a0c549f4]) UVM_INFO @ 206263291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56701805480880230345377537259110288759041336877054044162728207358035349872774	130	UVM_FATAL @ 175462553 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 130195445010078627110470706271177512841 [0x61f2bb09b36ade8232238765a3ed9789]) UVM_INFO @ 175462553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	30567196557554851706677196573434750985260496092122638073984661542937535507359	130	UVM_FATAL @ 242418192 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 167849610444199768755066991531998604133 [0x7e46a8ba2d143c822944740516a86b65]) UVM_INFO @ 242418192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32063691002831541165201231710088515070854916391606516103977076951794167963430	130	UVM_FATAL @ 89693504 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 325414794479250784203793801414216237140 [0xf4d09c1585fc45aae34958a98cdbc054]) UVM_INFO @ 89693504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	84859103661202689211068963633899814353954316233949476830910156970511640174174	130	UVM_FATAL @ 201225992 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 259587924861671646650559730314562602097 [0xc34ad0d640cedfe13973cb867c2d8471]) UVM_INFO @ 201225992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	53910778324249294486004205910345924199572370414679150420606467691891634060638	130	UVM_FATAL @ 101231460 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 66441804774944346557553100770184679831 [0x31fc39e4260324c6ecf6d2fc8cae5197]) UVM_INFO @ 101231460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	3743742296805333514513015928731223419827199618799871093513072635293200324808	130	UVM_FATAL @ 103238082 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 232104658666259291418830048664743667402 [0xae9dbb32437fc39e62f75fa6347d66ca]) UVM_INFO @ 103238082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	115631989996317166985746438509750568088266289849818332600046068296639694161068	130	UVM_FATAL @ 268177165 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 169394531827368667707197076474978663378 [0x7f70333b7820282f95acf2e480bc7bd2]) UVM_INFO @ 268177165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	34676866366544798834601317186240037950650493577448558982642823514000375158430	130	UVM_FATAL @ 27379541 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 302119107594040159079080691387426677252 [0xe34a060b381c36c533c9f59bd13c2204]) UVM_INFO @ 27379541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96329729780084237391451611862722361160933423114858773436914206641491514961252	130	UVM_FATAL @ 197338099 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 127265613659607377805111418855786129782 [0x5fbe77331ed2ff3298e61e9d567da976]) UVM_INFO @ 197338099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	14338172105505229551954867089466610597135892447727839907127951150680579980062	130	UVM_FATAL @ 32451011 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 192579907469608354091020504531712187993 [0x90e18a82244407379a7cdabfd2c99e59]) UVM_INFO @ 32451011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48836306973446570105206317048358705917733321590128474737206374983815740133422	130	UVM_FATAL @ 37026462 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 101181519530064392757498238243047571702 [0x4c1eda1168f4cc1af32ea010021180f6]) UVM_INFO @ 37026462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41213768156436272522994485380418219733347986701975296140081078357642705415565	130	UVM_FATAL @ 327248771 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 42114322506479883468114321240266581743 [0x1faeec693425ca3220ab5538280f26ef]) UVM_INFO @ 327248771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	21412316940219296522121554859647899407369441235199245801910123944379020495793	130	UVM_FATAL @ 214323632 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 188852947641858773232080798107441961835 [0x8e13c133afc59a778c822a3d8a5a1b6b]) UVM_INFO @ 214323632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83380255931686091632956784604817774710939477539551759860800881474294184548020	130	UVM_FATAL @ 833996543 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 221567112506541723786357406678104715265 [0xa6b0460f069ec83a7f5211e864b0b001]) UVM_INFO @ 833996543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	109192581617108819508549658786044972702436592300335273591279866284136059998025	130	UVM_FATAL @ 30539007 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 93148449165807020669881683229636622029 [0x4613bd1edca8cfa3b3dcbff5febcf6cd]) UVM_INFO @ 30539007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47904895122462510879352467187777436745846142927307673558719471035058243079712	140	UVM_FATAL @ 156486970 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 94107645288398769899877940442516195020 [0x46cc792401bcbe4574676cab72ec86cc]) UVM_INFO @ 156486970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	34500278065950347642243421495193169514445070200705419497654318225798162791320	130	UVM_FATAL @ 110896808 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 98464509479812959988830261961890266310 [0x4a139321494515a9ec3fa924004cfcc6]) UVM_INFO @ 110896808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	5276671434760874539795588291465924203238829856963834284408787784255779513213	140	UVM_FATAL @ 312852886 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 225812095407433935802856888391479368975 [0xa9e1d3dfe32bee31d6e6ad6e24f09d0f]) UVM_INFO @ 312852886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	87366861289871712748850897789769840622753916396123183665756443714719665426488	130	UVM_FATAL @ 54311276 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 44893017331119568091901890603522150779 [0x21c614a4a38d2c065bd370023bbf517b]) UVM_INFO @ 54311276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90663606849734250328075236749294493388028156036441820848993979198583557921130	130	UVM_FATAL @ 346116031 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 216655115670946874234336525218636028100 [0xa2fe41eab400e6a2818bc37d346ad8c4]) UVM_INFO @ 346116031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48466341361850200378619058842646425317175643433693254642981792098028060719312	130	UVM_FATAL @ 152842607 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 79287424994045216168653705961628087594 [0x3ba633dda7b68efd986617579c05b52a]) UVM_INFO @ 152842607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	36082917520135035529156597920398337535930932653893566202201967005510442316678	130	UVM_FATAL @ 157898899 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 310127690112207306154341968254124549084 [0xe9506ba5b23f2efd3d166068b3f5e3dc]) UVM_INFO @ 157898899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	111711047912047965200143706610856170286314209655359053170147712034420450344482	130	UVM_FATAL @ 69573968 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 11220437599856973311894296203012690902 [0x870fa48fdf2b6fe044e1734812953d6]) UVM_INFO @ 69573968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	27262965738643377127125317111708836446766692683688075484783502172017767257925	130	UVM_FATAL @ 12208671 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 29145796143305988326625164841127718869 [0x15ed46b2105d84dd3ab37b861d532fd5]) UVM_INFO @ 12208671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55755126483172395787333280419997253732247971541102508011202274441135910382188	130	UVM_FATAL @ 28074908 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 14181123239287352362949324558342883162 [0xaab2f5b7313b02ccbc3cf879afd075a]) UVM_INFO @ 28074908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46969046514243392368608193746906591248253182575136456903656401943875518295140	130	UVM_FATAL @ 103329266 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 84815359368109426975089712254414390156 [0x3fced812af31ee1942d1fca1b97a838c]) UVM_INFO @ 103329266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	84461404280715823505897114372787328881403532064483626957218525823438225769025	130	UVM_FATAL @ 54850222 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 320359164041626067168769643468821172737 [0xf102ee4244802098aa9a434332491201]) UVM_INFO @ 54850222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17624701346171516242081796884039809859687749987366136003808743580549724451334	130	UVM_FATAL @ 257070160 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 253808640481768933527530961274565492013 [0xbef1c41e2240cdb7cc7ad7c42bf2fd2d]) UVM_INFO @ 257070160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	74527169517092665004739730250905541839738750751565463062568400783882015885817	130	UVM_FATAL @ 18722592 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 245622135633574467186046710418926122069 [0xb8c91a4421aaf95d5de327ea09eeb455]) UVM_INFO @ 18722592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	63658138798879807508962363163732778671613751493223622791676490353840261390955	130	UVM_FATAL @ 25785743 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 292121139616441179731718169609374867260 [0xdbc47c2a1cc055be52bbe3e164b11f3c]) UVM_INFO @ 25785743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110045478517158781601238972420124050555420308067517765457658931115986280117297	130	UVM_FATAL @ 239672197 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 311148424565459679867523454452110086514 [0xea1501bdc5d6763a967fb7fc172a5172]) UVM_INFO @ 239672197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	97048285063070323777871389430636203258716282383399578538513192157630070279970	130	UVM_FATAL @ 100670107 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 112654576669787756903809183127493777146 [0x54c07b7543a90ea8ed37031985bd96fa]) UVM_INFO @ 100670107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46000994961379397451796708879882654679080177365693271437988431834395855326399	150	UVM_FATAL @ 1646141990 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 237621308963092308353938649609160032224 [0xb2c4330e36fef0e780e6220be7eeffe0]) UVM_INFO @ 1646141990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107889248838100647952540136886413834320168581355988349588262117824674956977675	130	UVM_FATAL @ 92580160 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 202665492518104912162957392582283866477 [0x9877f43e288711847088ffa808e7b16d]) UVM_INFO @ 92580160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	18769983571454808396042728040745049362582791604496022949881965055397070991513	130	UVM_FATAL @ 104825870 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 126203164214247260454086536085218930120 [0x5ef1d865d22763f70ed2c0bca8922dc8]) UVM_INFO @ 104825870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	89359793819386191595323507193684181413684034128816322102152392702240517639097	130	UVM_FATAL @ 87388881 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 304747174163695828516093715677630825407 [0xe5442bbaca021ff09c367e504d2203bf]) UVM_INFO @ 87388881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45988648089555637343847628482694321028687900775936347094116665670460350260087	130	UVM_FATAL @ 972888255 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 277630278967941202202785044608009460223 [0xd0dda592ef418f4682b780a3c56559ff]) UVM_INFO @ 972888255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	11520240735231382220940552213927332104755183585739248505679486278001991146482	130	UVM_FATAL @ 36013431 ps: (csrng_scoreboard.sv:660) [uvm_test_top.env.scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (0 [0x0] vs 76792748643552881209175427090784550280 [0x39c5bed3598cc1e27edb6e2223757d88]) UVM_INFO @ 36013431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	csrng_stress_all_with_rand_reset	2538191015003584815612758070147365155873964751061959535595273038256792293274	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	2314159834485081471100885485239984387079686611750988972419990163750808340195	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	4979899442628033376191278636741232060265623242695457426966370098718871014929	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	32195416497430172733511185371541248661460450578605430769617098660830908426182	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	105746190342326963937728019380274596140476813761940393704439012092635530692644	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	52140099500075579884089020858696596314056837936589986393958443188303737683671	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	110604514027481509620522272280545233132946428674830261345914541857581790420929	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	40780942935214120753683263205168439626189403072798899675348504862019978309846	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	91351048495021038332412257567822250516630598778516951455442194058742632909896	None	Job timed out after 180 minutes
	csrng_stress_all_with_rand_reset	80092225429253889331498162649407242645432160689434775887431060465289629958240	None	Job timed out after 180 minutes
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly
	csrng_cmds	107543084730041647011659587387808588643801914736760197360107802865871443183498	138	UVM_ERROR @ 130714391 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly UVM_INFO @ 130714391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	102953188847761338871597273936995051605884070362782480234295674114567731209533	138	UVM_ERROR @ 8678433 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly UVM_INFO @ 8678433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65577345844586091087474904652423566489697577891529553922591377138346902215996	138	UVM_ERROR @ 36139653 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly UVM_INFO @ 36139653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	113623475202223876638629478968298857957622574544922619705682028786005647092699	148	UVM_ERROR @ 153917367 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly UVM_INFO @ 153917367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits
	csrng_cmds	93723123818519757499328280451389928840936186409593536901258225464942228899955	133	UVM_ERROR @ 187068790 ps: (csrng_scoreboard.sv:418) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2075255943 [0x7bb1e487] vs 0 [0x0]) reg name: csrng_reg_block.genbits UVM_INFO @ 187068790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq
	csrng_stress_all	60423093593176620491103700874317856797186510889227386800464095493169686012608	152	UVM_ERROR @ 4480932323 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq UVM_INFO @ 4480932323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])
	csrng_cmds	109965669773045902777267009304019450426478857500627163448756554776114598834512	139	UVM_FATAL @ 96961295 ps: (csrng_scoreboard.sv:629) [uvm_test_top.env.scoreboard] Check failed cs_item[app].status == cmd_sts[app] (0 [0x0] vs 3 [0x3]) UVM_INFO @ 96961295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---