Simulation Results: edn/edn0

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 96.06 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 93.55 %
Validation stages
V1
100.00%
V2
98.97%
V2S
100.00%
V3
86.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.370s 18.483us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.190s 22.677us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.290s 134.233us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 6.160s 430.775us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.570s 36.320us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.830s 26.146us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.290s 134.233us 20 20 100.00
edn_csr_aliasing 1.570s 36.320us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 52.410s 4396.749us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 52.410s 4396.749us 300 300 100.00
genbits 300 300 100.00
edn_genbits 52.410s 4396.749us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.250s 20.984us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.510s 112.811us 200 200 100.00
errs 100 100 100.00
edn_err 1.590s 20.674us 100 100 100.00
disable 90 100 90.00
edn_disable 2.770s 500.000us 49 50 98.00
edn_disable_auto_req_mode 4.510s 500.000us 41 50 82.00
stress_all 50 50 100.00
edn_stress_all 4.860s 342.739us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.270s 17.216us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.360s 45.058us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 4.840s 1446.422us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 4.840s 1446.422us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.190s 22.677us 5 5 100.00
edn_csr_rw 1.290s 134.233us 20 20 100.00
edn_csr_aliasing 1.570s 36.320us 5 5 100.00
edn_same_csr_outstanding 1.870s 136.502us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.190s 22.677us 5 5 100.00
edn_csr_rw 1.290s 134.233us 20 20 100.00
edn_csr_aliasing 1.570s 36.320us 5 5 100.00
edn_same_csr_outstanding 1.870s 136.502us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 7.960s 711.843us 5 5 100.00
edn_tl_intg_err 3.130s 172.670us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.000s 17.559us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.510s 112.811us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.960s 711.843us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.960s 711.843us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.960s 711.843us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.960s 711.843us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.510s 112.811us 200 200 100.00
edn_sec_cm 7.960s 711.843us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.510s 112.811us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.130s 172.670us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 43 50 86.00
edn_stress_all_with_rand_reset 96.240s 21775.811us 43 50 86.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 89247582964981813985841287126012293526939965928942480513975594827981344424861 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 82897666948832011784727961287879098255670207605397244446965079425715548702751 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 110337804648961586732006758503461308331945456534206844195215653162826674651147 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 5773208278996620726926769153631335785324737653304051527049035903325632735075 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 82767901500991349280478485996407241407965088745310609657134223796278891660694 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable 101428617399008641556255590568250287251413807187149924800284871655737939735849 85
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 21153544478899922663363176366949091188082677040438919935116540508748559343209 161
UVM_ERROR @ 133767343 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 133767343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 99705056707227310680786173238660791085560619821765730946092820301444069930309 252
UVM_ERROR @ 2841032770 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2841032770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 31968574177855047975279060390862854185588383544323871020522148663320945279662 234
UVM_ERROR @ 1721637877 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1721637877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 81576317555565182668366445549420218564226373456213634384485233416649982315530 124
UVM_ERROR @ 721187385 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 721187385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 55075741379379228080331345554752028994270656747656945293814795475788306200031 175
UVM_ERROR @ 1330604238 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1330604238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 72390433690246532303611007671315432118402585024883975006168062448005140093834 88
UVM_FATAL @ 10733486 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0078b672 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 10733486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 96252986819345380219902718723433556839598260911231239809695931986955317706647 88
UVM_FATAL @ 26786078 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x009bd612 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 26786078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 81230352419028174938061396340977199998052361762998409443481242172528067268330 88
UVM_FATAL @ 22288613 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00d0f602 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 22288613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 49845509306843815143629636398939959442772687063206474179155375381060868253437 88
UVM_FATAL @ 61073302 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x007c3962 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 61073302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_stress_all_with_rand_reset 65596773103212693652390540483779502997900366815309657514573538396495425508265 229
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1091660117 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 75056374343408699837410757311938529838198479364652286493473200807566985051549 114
UVM_ERROR @ 227548747 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 227548747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---