Simulation Results: edn/edn1

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 96.36 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.85 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
99.28%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.060s 22.953us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.880s 23.418us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.850s 100.160us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.660s 224.308us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.250s 42.340us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.540s 36.216us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.850s 100.160us 20 20 100.00
edn_csr_aliasing 1.250s 42.340us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 3.820s 690.529us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 3.820s 690.529us 300 300 100.00
genbits 300 300 100.00
edn_genbits 3.820s 690.529us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.210s 37.809us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.370s 24.229us 200 200 100.00
errs 100 100 100.00
edn_err 1.280s 25.495us 100 100 100.00
disable 93 100 93.00
edn_disable 1.010s 11.992us 50 50 100.00
edn_disable_auto_req_mode 5.610s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 4.180s 288.393us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.820s 54.242us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.130s 16.423us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.120s 144.425us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.120s 144.425us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.880s 23.418us 5 5 100.00
edn_csr_rw 0.850s 100.160us 20 20 100.00
edn_csr_aliasing 1.250s 42.340us 5 5 100.00
edn_same_csr_outstanding 1.120s 62.857us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.880s 23.418us 5 5 100.00
edn_csr_rw 0.850s 100.160us 20 20 100.00
edn_csr_aliasing 1.250s 42.340us 5 5 100.00
edn_same_csr_outstanding 1.120s 62.857us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 3.390s 1368.469us 5 5 100.00
edn_tl_intg_err 7.500s 815.189us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.860s 17.943us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.370s 24.229us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.390s 1368.469us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.390s 1368.469us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.390s 1368.469us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.390s 1368.469us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.370s 24.229us 200 200 100.00
edn_sec_cm 3.390s 1368.469us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.370s 24.229us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 7.500s 815.189us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 45 50 90.00
edn_stress_all_with_rand_reset 109.930s 13008.808us 45 50 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 34091134756022713980321331301151619065196930039565012080392266157079975211965 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 10595228201651990060389895064783294691334318733939451751836096779828173353406 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72042321932904139822931240202392027256633132408200531780474463294921063986271 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 36322323385481769537886626384446751343537205857103721633289534843757860137862 89
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 7707511711506133398919780476346359913180140209902896424429266504483211985441 88
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 48537800225862101237219873758417643261557869056545095880349899338158871509151 164
UVM_ERROR @ 1284191348 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1284191348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 100816091430366554803661073886271834034193289986521050641579864757561708751195 140
UVM_ERROR @ 922455641 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 922455641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 65281029300144008258081548564843528260941737697529240260212467313915604197741 155
UVM_ERROR @ 1245501796 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1245501796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 78252976802965608836413799284697237069929318072658037975214981148608625315416 174
UVM_ERROR @ 1519631536 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1519631536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.
edn_disable_auto_req_mode 90262370118770608927859282232680736109693659881733659733103489489328462878231 88
UVM_FATAL @ 49940000 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0069e952 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 49940000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 27104128750241176382139563474004783119591350653882512012003946427493395301045 88
UVM_FATAL @ 24823823 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00de2902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx.
UVM_INFO @ 24823823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit
edn_stress_all_with_rand_reset 74485761904261113210805836453352536987680822552426363118591794149988342088794 248
Error-[FCIBH] Illegal bin hit
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2276210470 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup