Simulation Results: hmac

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.83 %
  • code
  • 98.73 %
  • assert
  • 97.80 %
  • func
  • 99.95 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.770s 809.876us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.080s 89.944us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.290s 58.720us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.610s 3668.789us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 6.710s 609.549us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 691.860s 171226.690us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.290s 58.720us 20 20 100.00
hmac_csr_aliasing 6.710s 609.549us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 129.390s 41974.548us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 87.970s 7141.851us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 296.900s 104784.390us 30 30 100.00
hmac_test_sha384_vectors 578.040s 59829.649us 75 75 100.00
hmac_test_sha512_vectors 545.110s 54342.035us 75 75 100.00
hmac_test_hmac256_vectors 14.780s 314.335us 50 50 100.00
hmac_test_hmac384_vectors 16.530s 6124.746us 60 60 100.00
hmac_test_hmac512_vectors 20.580s 456.996us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 37.130s 1540.593us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1528.950s 30920.879us 10 10 100.00
error 10 10 100.00
hmac_error 143.970s 57948.263us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 134.380s 39580.855us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.770s 809.876us 10 10 100.00
hmac_long_msg 129.390s 41974.548us 10 10 100.00
hmac_back_pressure 87.970s 7141.851us 25 25 100.00
hmac_datapath_stress 1528.950s 30920.879us 10 10 100.00
hmac_burst_wr 37.130s 1540.593us 50 50 100.00
hmac_stress_all 2080.870s 289773.211us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.770s 809.876us 10 10 100.00
hmac_long_msg 129.390s 41974.548us 10 10 100.00
hmac_back_pressure 87.970s 7141.851us 25 25 100.00
hmac_datapath_stress 1528.950s 30920.879us 10 10 100.00
hmac_wipe_secret 134.380s 39580.855us 10 10 100.00
hmac_test_sha256_vectors 296.900s 104784.390us 30 30 100.00
hmac_test_sha384_vectors 578.040s 59829.649us 75 75 100.00
hmac_test_sha512_vectors 545.110s 54342.035us 75 75 100.00
hmac_test_hmac256_vectors 14.780s 314.335us 50 50 100.00
hmac_test_hmac384_vectors 16.530s 6124.746us 60 60 100.00
hmac_test_hmac512_vectors 20.580s 456.996us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.770s 809.876us 10 10 100.00
hmac_long_msg 129.390s 41974.548us 10 10 100.00
hmac_back_pressure 87.970s 7141.851us 25 25 100.00
hmac_datapath_stress 1528.950s 30920.879us 10 10 100.00
hmac_burst_wr 37.130s 1540.593us 50 50 100.00
hmac_error 143.970s 57948.263us 10 10 100.00
hmac_wipe_secret 134.380s 39580.855us 10 10 100.00
hmac_test_sha256_vectors 296.900s 104784.390us 30 30 100.00
hmac_test_sha384_vectors 578.040s 59829.649us 75 75 100.00
hmac_test_sha512_vectors 545.110s 54342.035us 75 75 100.00
hmac_test_hmac256_vectors 14.780s 314.335us 50 50 100.00
hmac_test_hmac384_vectors 16.530s 6124.746us 60 60 100.00
hmac_test_hmac512_vectors 20.580s 456.996us 75 75 100.00
hmac_stress_all 2080.870s 289773.211us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2080.870s 289773.211us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.950s 21.484us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.970s 19.565us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.130s 408.475us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.130s 408.475us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.080s 89.944us 5 5 100.00
hmac_csr_rw 1.290s 58.720us 20 20 100.00
hmac_csr_aliasing 6.710s 609.549us 5 5 100.00
hmac_same_csr_outstanding 2.290s 125.297us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.080s 89.944us 5 5 100.00
hmac_csr_rw 1.290s 58.720us 20 20 100.00
hmac_csr_aliasing 6.710s 609.549us 5 5 100.00
hmac_same_csr_outstanding 2.290s 125.297us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 4.310s 1109.128us 20 20 100.00
hmac_sec_cm 1.340s 116.174us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.310s 1109.128us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.770s 809.876us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 4.790s 205.042us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 755.270s 298907.681us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.940s 35.211us 1 1 100.00