Simulation Results

Simulation Results: kmac/masked

18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.83 %

code
94.67 %

assert
97.98 %

func
97.85 %

line
99.25 %

branch
97.08 %

cond
94.76 %

toggle
99.89 %

FSM
82.39 %

Validation stages

V1		98.26%
V2		99.61%
V2S		97.78%
V3		80.00%

113/115 passed

98.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				48	50	96.00
	kmac_smoke	89.450s	7333.022us	48	50	96.00
csr_hw_reset				5	5	100.00
	kmac_csr_hw_reset	1.570s	31.157us	5	5	100.00
csr_rw				20	20	100.00
	kmac_csr_rw	1.600s	34.617us	20	20	100.00
csr_bit_bash				5	5	100.00
	kmac_csr_bit_bash	19.540s	1271.653us	5	5	100.00
csr_aliasing				5	5	100.00
	kmac_csr_aliasing	9.430s	1584.130us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	kmac_csr_mem_rw_with_rand_reset	3.720s	1202.591us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	kmac_csr_rw	1.600s	34.617us	20	20	100.00
	kmac_csr_aliasing	9.430s	1584.130us	5	5	100.00
mem_walk				5	5	100.00
	kmac_mem_walk	1.100s	21.609us	5	5	100.00
mem_partial_access				5	5	100.00
	kmac_mem_partial_access	1.940s	73.644us	5	5	100.00

767/770 passed

99.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				50	50	100.00
	kmac_long_msg_and_output	3506.060s	255684.689us	50	50	100.00
burst_write				50	50	100.00
	kmac_burst_write	1355.460s	37757.416us	50	50	100.00
test_vectors				40	40	100.00
	kmac_test_vectors_sha3_224	2083.690s	521426.596us	5	5	100.00
	kmac_test_vectors_sha3_256	1805.750s	61092.655us	5	5	100.00
	kmac_test_vectors_sha3_384	1482.250s	47480.281us	5	5	100.00
	kmac_test_vectors_sha3_512	1200.380s	32954.634us	5	5	100.00
	kmac_test_vectors_shake_128	2443.350s	92952.835us	5	5	100.00
	kmac_test_vectors_shake_256	1479.850s	71605.314us	5	5	100.00
	kmac_test_vectors_kmac	3.350s	171.281us	5	5	100.00
	kmac_test_vectors_kmac_xof	3.930s	517.434us	5	5	100.00
sideload				49	50	98.00
	kmac_sideload	521.190s	41601.383us	49	50	98.00
app				50	50	100.00
	kmac_app	384.980s	56462.730us	50	50	100.00
app_with_partial_data				10	10	100.00
	kmac_app_with_partial_data	243.840s	19456.929us	10	10	100.00
entropy_refresh				50	50	100.00
	kmac_entropy_refresh	385.490s	21649.858us	50	50	100.00
error				49	50	98.00
	kmac_error	489.610s	17096.553us	49	50	98.00
key_error				50	50	100.00
	kmac_key_error	17.950s	6591.801us	50	50	100.00
sideload_invalid				50	50	100.00
	kmac_sideload_invalid	9.820s	337.581us	50	50	100.00
edn_timeout_error				20	20	100.00
	kmac_edn_timeout_error	46.470s	14291.379us	20	20	100.00
entropy_mode_error				20	20	100.00
	kmac_entropy_mode_error	37.390s	624.793us	20	20	100.00
entropy_ready_error				10	10	100.00
	kmac_entropy_ready_error	76.470s	8451.186us	10	10	100.00
lc_escalation				50	50	100.00
	kmac_lc_escalation	49.710s	3003.862us	50	50	100.00
stress_all				49	50	98.00
	kmac_stress_all	2336.840s	395008.958us	49	50	98.00
intr_test				50	50	100.00
	kmac_intr_test	1.200s	18.630us	50	50	100.00
alert_test				50	50	100.00
	kmac_alert_test	1.280s	193.702us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	kmac_tl_errors	4.020s	485.613us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	kmac_tl_errors	4.020s	485.613us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	kmac_csr_hw_reset	1.570s	31.157us	5	5	100.00
	kmac_csr_rw	1.600s	34.617us	20	20	100.00
	kmac_csr_aliasing	9.430s	1584.130us	5	5	100.00
	kmac_same_csr_outstanding	3.080s	92.994us	20	20	100.00
tl_d_partial_access				50	50	100.00
	kmac_csr_hw_reset	1.570s	31.157us	5	5	100.00
	kmac_csr_rw	1.600s	34.617us	20	20	100.00
	kmac_csr_aliasing	9.430s	1584.130us	5	5	100.00
	kmac_same_csr_outstanding	3.080s	92.994us	20	20	100.00

V2S

220/225 passed

97.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	kmac_shadow_reg_errors	2.770s	88.236us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	kmac_shadow_reg_errors	2.770s	88.236us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	kmac_shadow_reg_errors	2.770s	88.236us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	kmac_shadow_reg_errors	2.770s	88.236us	20	20	100.00
shadow_reg_update_error_with_csr_rw				18	20	90.00
	kmac_shadow_reg_errors_with_csr_rw	6.160s	251.118us	18	20	90.00
tl_intg_err				25	25	100.00
	kmac_sec_cm	103.990s	7650.563us	5	5	100.00
	kmac_tl_intg_err	4.840s	432.706us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	kmac_tl_intg_err	4.840s	432.706us	20	20	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	kmac_lc_escalation	49.710s	3003.862us	50	50	100.00
sec_cm_sw_key_key_masking				48	50	96.00
	kmac_smoke	89.450s	7333.022us	48	50	96.00
sec_cm_key_sideload				49	50	98.00
	kmac_sideload	521.190s	41601.383us	49	50	98.00
sec_cm_cfg_shadowed_config_shadow				20	20	100.00
	kmac_shadow_reg_errors	2.770s	88.236us	20	20	100.00
sec_cm_fsm_sparse				5	5	100.00
	kmac_sec_cm	103.990s	7650.563us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	kmac_sec_cm	103.990s	7650.563us	5	5	100.00
sec_cm_packer_ctr_redun				5	5	100.00
	kmac_sec_cm	103.990s	7650.563us	5	5	100.00
sec_cm_cfg_shadowed_config_regwen				48	50	96.00
	kmac_smoke	89.450s	7333.022us	48	50	96.00
sec_cm_fsm_global_esc				50	50	100.00
	kmac_lc_escalation	49.710s	3003.862us	50	50	100.00
sec_cm_fsm_local_esc				5	5	100.00
	kmac_sec_cm	103.990s	7650.563us	5	5	100.00
sec_cm_absorbed_ctrl_mubi				10	10	100.00
	kmac_mubi	322.230s	81250.500us	10	10	100.00
sec_cm_sw_cmd_ctrl_sparse				48	50	96.00
	kmac_smoke	89.450s	7333.022us	48	50	96.00

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				8	10	80.00
	kmac_stress_all_with_rand_reset	185.980s	6605.113us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [] vs [*])
	kmac_stress_all_with_rand_reset	71763475276560364819062926783685922270909938581182482614735192405141003801364	394	UVM_ERROR @ 6605113087 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0]) UVM_INFO @ 6605113087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	11770776195038600560744947061786863032130430963277552913106031758884975948970	226	UVM_ERROR @ 20864622308 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0]) UVM_INFO @ 20864622308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	kmac_error	41612379237983874876421010883236247468815095167545207353538155217301768895563	180	UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: kmac_reg_block.intr_state.kmac_done reset value:
	kmac_smoke	25226997705193681046646265037102457085764861725318904698435879280563856777288	77	UVM_ERROR @ 82048050 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0 UVM_INFO @ 82048050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_smoke	63801194574227784842227187179320775386404611337622934227325877535699150677133	77	UVM_ERROR @ 58196641 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0 UVM_INFO @ 58196641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload	46442283066759651621873396242902316674843246553746922438969877359883078531512	77	UVM_ERROR @ 274325372 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0 UVM_INFO @ 274325372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all	108642460732483562236379691055380744082728268566980457376839020503175721052688	189	UVM_ERROR @ 8106154768 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0 UVM_INFO @ 8106154768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: kmac_reg_block.prefix_.prefix_* reset value: *
	kmac_shadow_reg_errors_with_csr_rw	39515173965964633787981851994841438189817149096571066663499898988145964543203	315	UVM_ERROR @ 74888210 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2314890256 [0x89fa6c10] vs 0 [0x0]) Regname: kmac_reg_block.prefix_9.prefix_0 reset value: 0x0 UVM_INFO @ 74888210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: kmac_reg_block.prefix_ reset value: *
	kmac_shadow_reg_errors_with_csr_rw	73801401178018845869504346992871800916494630390803467012597294152562704027304	432	UVM_ERROR @ 253538754 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3568069806 [0xd4ac6cae] vs 975364252 [0x3a22e09c]) Regname: kmac_reg_block.prefix_4 reset value: 0x0 UVM_INFO @ 253538754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---