Simulation Results: kmac/unmasked

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 92.21 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.31%
V2S
99.11%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 64.730s 8425.906us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.270s 52.656us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.350s 315.711us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.780s 3453.581us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.450s 523.571us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.340s 40.597us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.350s 315.711us 20 20 100.00
kmac_csr_aliasing 7.450s 523.571us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.040s 12.493us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.930s 80.651us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2822.640s 412961.255us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 877.780s 500000.000us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1849.650s 380820.841us 5 5 100.00
kmac_test_vectors_sha3_256 1270.940s 16977.040us 5 5 100.00
kmac_test_vectors_sha3_384 1405.550s 46290.938us 5 5 100.00
kmac_test_vectors_sha3_512 720.740s 37938.609us 5 5 100.00
kmac_test_vectors_shake_128 2190.350s 285765.535us 5 5 100.00
kmac_test_vectors_shake_256 327.450s 51466.407us 5 5 100.00
kmac_test_vectors_kmac 2.720s 144.943us 5 5 100.00
kmac_test_vectors_kmac_xof 3.430s 447.549us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 483.650s 126381.754us 50 50 100.00
app 50 50 100.00
kmac_app 334.930s 284932.097us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 359.720s 169306.175us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 350.710s 279149.093us 50 50 100.00
error 49 50 98.00
kmac_error 385.070s 19451.199us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 15.340s 17874.583us 50 50 100.00
sideload_invalid 39 50 78.00
kmac_sideload_invalid 125.000s 10034.860us 39 50 78.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 40.890s 2268.256us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 37.990s 13950.433us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 53.210s 5176.327us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 56.370s 3576.110us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3671.910s 111694.520us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.150s 26.737us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.290s 142.564us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.470s 1465.462us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.470s 1465.462us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.270s 52.656us 5 5 100.00
kmac_csr_rw 1.350s 315.711us 20 20 100.00
kmac_csr_aliasing 7.450s 523.571us 5 5 100.00
kmac_same_csr_outstanding 2.610s 86.498us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.270s 52.656us 5 5 100.00
kmac_csr_rw 1.350s 315.711us 20 20 100.00
kmac_csr_aliasing 7.450s 523.571us 5 5 100.00
kmac_same_csr_outstanding 2.610s 86.498us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.410s 283.172us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.410s 283.172us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.410s 283.172us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.410s 283.172us 20 20 100.00
shadow_reg_update_error_with_csr_rw 18 20 90.00
kmac_shadow_reg_errors_with_csr_rw 4.530s 404.953us 18 20 90.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.930s 342.186us 20 20 100.00
kmac_sec_cm 55.860s 3698.703us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.930s 342.186us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 56.370s 3576.110us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 64.730s 8425.906us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 483.650s 126381.754us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.410s 283.172us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 55.860s 3698.703us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 55.860s 3698.703us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 55.860s 3698.703us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 64.730s 8425.906us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 56.370s 3576.110us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 55.860s 3698.703us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 311.590s 18994.939us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 64.730s 8425.906us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 211.560s 4367.470us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: *
kmac_shadow_reg_errors_with_csr_rw 10310529192525336925367915805752261986613423701273911078910821990882584204881 103
UVM_ERROR @ 4679274 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (954 [0x3ba] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
UVM_INFO @ 4679274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 69491741703506664711401114914972742700623207269007827569124511990458411666581 116
UVM_ERROR @ 4484891 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (2792694041 [0xa6752119] vs 762944777 [0x2d799d09]) Regname: kmac_reg_block.prefix_10.prefix_0 reset value: 0x0
UVM_INFO @ 4484891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 2898406833308082730798040530158164075286196011872235436838160045201163096384 211
UVM_ERROR @ 8202764835 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 8202764835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 46915447579304821542962456806761527686530281163609508679598507533077969483161 385
UVM_ERROR @ 19886610632 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 19886610632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 109725296995121027269139430561712473831370917066810166131007066229754031233540 87
UVM_FATAL @ 10047620194 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x49347000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10047620194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 202700382688278468114758507044517917653089380011987625458834678392976246551 86
UVM_FATAL @ 10495870396 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc5be4000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10495870396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 110278348857372462289340931043946220567062707060275371880332853886835157802603 84
UVM_FATAL @ 10137417553 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9cf8000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10137417553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 43321365940580597457055143619232970908223319413202339090857848044499231069642 85
UVM_FATAL @ 10311920988 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x46436000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10311920988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 57591341032244390708366791692546329161217825736952946896592194345736459221134 253
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 62585382051025709256292763048874476331455550205617360770966791462964624173105 190
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 61164887828735756587657294386408739300669216047974829603429753341246084416709 79
UVM_FATAL @ 10077538251 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6021c000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10077538251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 13662082494016450972528650785984742434012161260097101937027719815861720504515 80
UVM_FATAL @ 10034860243 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe695c000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10034860243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 111789664065765745947687043787692711796904370151669629514845752469204728417024 81
UVM_FATAL @ 10079675761 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xecb89000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10079675761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 87401473282389699670070696118508943179144406805615639370344928015706804857588 81
UVM_FATAL @ 10022709924 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6ed04000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10022709924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 34545026991425551901561843898477045343343542112809463943474169943280859935938 94
UVM_FATAL @ 10219902495 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x89a0c000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10219902495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 7326285060460766041236836971460658170517003030142596598861152127037321415284 82
UVM_FATAL @ 10114909212 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc9810000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10114909212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 1229653819071603584443815641374644827149979780595427317575669150514795667866 87
UVM_FATAL @ 10365418483 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb9dec000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10365418483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---