Simulation Results: otbn

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.92 %
  • code
  • 96.69 %
  • assert
  • 97.06 %
  • func
  • 100.00 %
  • block
  • 99.48 %
  • line
  • 99.64 %
  • branch
  • 93.33 %
  • toggle
  • 93.81 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.91%
V2S
97.94%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 229.756us 1 1 100.00
single_binary 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 12.000s 28.235us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 10.000s 25.636us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 15.000s 611.870us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 10.000s 53.116us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 11.000s 81.171us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 10.000s 25.636us 20 20 100.00
otbn_csr_aliasing 10.000s 53.116us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 131.000s 20692.546us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 51.000s 11626.543us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 9 10 90.00
otbn_reset 53.000s 199.707us 9 10 90.00
multi_error 1 1 100.00
otbn_multi_err 96.000s 427.424us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 186.000s 683.872us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 98.000s 439.303us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 36.000s 127.020us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 11.000s 41.806us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 31.000s 65.961us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 8.000s 27.330us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 10.000s 105.827us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 12.000s 93.096us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 12.000s 93.096us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 12.000s 28.235us 5 5 100.00
otbn_csr_rw 10.000s 25.636us 20 20 100.00
otbn_csr_aliasing 10.000s 53.116us 5 5 100.00
otbn_same_csr_outstanding 9.000s 34.116us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 12.000s 28.235us 5 5 100.00
otbn_csr_rw 10.000s 25.636us 20 20 100.00
otbn_csr_aliasing 10.000s 53.116us 5 5 100.00
otbn_same_csr_outstanding 9.000s 34.116us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 24 25 96.00
otbn_imem_err 10.000s 48.817us 10 10 100.00
otbn_dmem_err 15.000s 48.903us 14 15 93.33
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 14.000s 114.708us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 63.568us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 66.979us 5 5 100.00
otbn_urnd_err 6.000s 17.790us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 6.000s 10.512us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 70.156us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 9.000s 37.704us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 33.000s 182.571us 20 20 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
passthru_mem_tl_intg_err 20 20 100.00
otbn_passthru_mem_tl_intg_err 56.000s 672.273us 20 20 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 229.756us 1 1 100.00
sec_cm_data_mem_integrity 14 15 93.33
otbn_dmem_err 15.000s 48.903us 14 15 93.33
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 10.000s 48.817us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 33.000s 182.571us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 36.000s 127.020us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 10.000s 48.817us 10 10 100.00
otbn_dmem_err 15.000s 48.903us 14 15 93.33
otbn_zero_state_err_urnd 11.000s 41.806us 5 5 100.00
otbn_illegal_mem_acc 6.000s 10.512us 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 10.000s 48.817us 10 10 100.00
otbn_dmem_err 15.000s 48.903us 14 15 93.33
otbn_zero_state_err_urnd 11.000s 41.806us 5 5 100.00
otbn_illegal_mem_acc 6.000s 10.512us 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 36.000s 127.020us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 10.000s 48.817us 10 10 100.00
otbn_dmem_err 15.000s 48.903us 14 15 93.33
otbn_zero_state_err_urnd 11.000s 41.806us 5 5 100.00
otbn_illegal_mem_acc 6.000s 10.512us 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 9.000s 28.057us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 3 5 60.00
otbn_pc_ctrl_flow_redun 10.787s 0.000us 3 5 60.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 108.000s 1761.469us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 108.000s 1761.469us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 15.000s 54.755us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 53.000s 823.432us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 154.000s 613.539us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 154.000s 613.539us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 11.000s 56.658us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 186.000s 683.872us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 13.000s 105.204us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 220.000s 733.384us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 320.000s 1520.748us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 551.000s 1644.620us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 109.866us 1 1 100.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_reset 43892681636600802591736806699621195778039501388820510104369744005716833657045 None
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 43892681636600802591736806699621195778039501388820510104369744005716833657045 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_reset/latest
2026/04/18 20:49:53 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
otbn_pc_ctrl_flow_redun 24188219880294877684669301280691092174739683867065048401673163905523845825733 None
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 24188219880294877684669301280691092174739683867065048401673163905523845825733 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_pc_ctrl_flow_redun/latest
2026/04/18 20:49:56 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
otbn_escalate 26479033609359205410144277204223152615141457254811447764931642603141300667083 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 95121252343489715817780908262121181820802233531890281902696674371788407411458 166
UVM_ERROR @ 430186059 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 430186059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 21546585379011333416524494583533009678472133237416809297808213163603550881143 208
UVM_ERROR @ 266308504 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 266308504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 51135162766492305025133955795985671719180686383994710363433613856268799007075 200
UVM_ERROR @ 1529004239 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1529004239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 58325240422848059647015099025113663918471825308419571263869174977797914616115 245
UVM_ERROR @ 502009039 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 502009039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 16114865110384180932050729622055763568919417825657088490161284795113814648887 242
UVM_ERROR @ 731366088 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 731366088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 52948320123237536446966217892300000336612483446197147037865041691696751056960 117
UVM_ERROR @ 7536785 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 7536785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 84848965302717740493276809079583391259739042570378246900010334224544381037703 108
UVM_ERROR @ 1602799 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1602799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_pc_ctrl_flow_redun_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_pc_ctrl_flow_redun 22110367983672584627446059579226105017217637059966160266418628362792826884456 105
UVM_FATAL @ 35194908 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_pc_ctrl_flow_redun_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 35194908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_stress_all_with_rand_reset 86767025891186258891620572311149368460912943697313778172109223459088572183858 237
UVM_FATAL @ 294454964 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 294454964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:138) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
otbn_rf_base_intg_err 66243131783932851640739074078024918122733271053825862053278238999914486345526 116
UVM_FATAL @ 30326866 ps: (otbn_rf_base_intg_err_vseq.sv:138) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
UVM_INFO @ 30326866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_dmem_err 90346048770845679409348132741552169273010638978241400733043459121368950117849 103
UVM_FATAL @ 31312867 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 31312867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---