Simulation Results

Simulation Results: rom_ctrl/32kb

18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.59 %

code
99.68 %

assert
96.80 %

func
99.28 %

line
99.59 %

branch
100.00 %

cond
98.81 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		94.20%
V3		95.00%

67/67 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	7.680s	874.496us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	8.880s	177.826us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	6.950s	167.567us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	6.730s	534.655us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	7.090s	168.372us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	7.140s	316.102us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	6.950s	167.567us	20	20	100.00
	rom_ctrl_csr_aliasing	7.090s	168.372us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	5.360s	406.025us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	5.110s	206.854us	5	5	100.00

144/144 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	6.990s	202.835us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	29.290s	601.098us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	11.400s	390.050us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	9.140s	553.852us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	10.850s	535.140us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	10.850s	535.140us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	8.880s	177.826us	5	5	100.00
	rom_ctrl_csr_rw	6.950s	167.567us	20	20	100.00
	rom_ctrl_csr_aliasing	7.090s	168.372us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.400s	579.959us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	8.880s	177.826us	5	5	100.00
	rom_ctrl_csr_rw	6.950s	167.567us	20	20	100.00
	rom_ctrl_csr_aliasing	7.090s	168.372us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.400s	579.959us	20	20	100.00

V2S

65/69 passed

94.20 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	33.890s	5899.369us	20	20	100.00
tl_intg_err				25	25	100.00
	rom_ctrl_sec_cm	277.550s	761.487us	5	5	100.00
	rom_ctrl_tl_intg_err	64.560s	942.959us	20	20	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	277.550s	761.487us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	277.550s	761.487us	5	5	100.00
sec_cm_checker_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_checker_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_checker_fsm_local_esc				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_compare_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_compare_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	277.550s	761.487us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	277.550s	761.487us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	7.680s	874.496us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	7.680s	874.496us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	7.680s	874.496us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	64.560s	942.959us	20	20	100.00
sec_cm_bus_local_esc				18	22	81.82
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
	rom_ctrl_kmac_err_chk	11.400s	390.050us	2	2	100.00
sec_cm_mux_mubi				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_mux_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_ctrl_redun				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	131.350s	2471.738us	16	20	80.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	33.890s	5899.369us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	277.550s	761.487us	5	5	100.00

19/20 passed

95.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				19	20	95.00
	rom_ctrl_stress_all_with_rand_reset	446.770s	5309.149us	19	20	95.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	53673527693543778399727662241600378024414811284290567682237881264612364231580	107	UVM_ERROR @ 1089220957 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 1089220957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	18777696668184562330949179986306945190209044163505989334741986557913464655643	93	UVM_ERROR @ 1744860069 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 1744860069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	109608282550982886122555787732866274546245111356383908103313520139116104888934	78	UVM_ERROR @ 765634418 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 765634418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	60929281187148037854250204715312414367823084244017364174090484555912153219581	99	UVM_ERROR @ 786109776 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 786109776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
	rom_ctrl_stress_all_with_rand_reset	35390464084661180372786459367278680333610188055666820459083291293774170181970	88	UVM_ERROR @ 391181382 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire UVM_INFO @ 391181382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---