Simulation Results: rom_ctrl/64kb

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.05 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 9.840s 220.922us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 16.160s 12374.982us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 14.320s 1048.155us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 9.920s 218.678us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 9.790s 293.139us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.310s 312.620us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 14.320s 1048.155us 20 20 100.00
rom_ctrl_csr_aliasing 9.790s 293.139us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 9.420s 299.738us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 12.750s 9005.573us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 12.930s 953.640us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 45.580s 2745.996us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 18.310s 1422.845us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 14.500s 1079.775us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 15.030s 319.518us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 15.030s 319.518us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 16.160s 12374.982us 5 5 100.00
rom_ctrl_csr_rw 14.320s 1048.155us 20 20 100.00
rom_ctrl_csr_aliasing 9.790s 293.139us 5 5 100.00
rom_ctrl_same_csr_outstanding 12.890s 303.209us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 16.160s 12374.982us 5 5 100.00
rom_ctrl_csr_rw 14.320s 1048.155us 20 20 100.00
rom_ctrl_csr_aliasing 9.790s 293.139us 5 5 100.00
rom_ctrl_same_csr_outstanding 12.890s 303.209us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 70.660s 12450.537us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 571.610s 730.264us 5 5 100.00
rom_ctrl_tl_intg_err 120.520s 510.614us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 571.610s 730.264us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 571.610s 730.264us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 571.610s 730.264us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 571.610s 730.264us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 9.840s 220.922us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 9.840s 220.922us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 9.840s 220.922us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 120.520s 510.614us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
rom_ctrl_kmac_err_chk 18.310s 1422.845us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 243.200s 18770.445us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 70.660s 12450.537us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 571.610s 730.264us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 249.510s 7488.897us 19 20 95.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
rom_ctrl_stress_all_with_rand_reset 77095219039547585153515999084918858320164332598260449086720589484729283051954 102
UVM_ERROR @ 1316273877 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 1316273877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---