Simulation Results: rstmgr

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.59 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.49%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.610s 64.885us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.260s 94.525us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.270s 44.441us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 4.240s 176.235us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.560s 56.092us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.030s 99.580us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.270s 44.441us 20 20 100.00
rstmgr_csr_aliasing 1.560s 56.092us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 2.100s 166.239us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.510s 48.312us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.560s 91.349us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 7.430s 681.125us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 7.430s 681.125us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 7.430s 681.125us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 7.430s 681.125us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 53.510s 7010.574us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.550s 102.803us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.630s 73.250us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.630s 73.250us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.260s 94.525us 5 5 100.00
rstmgr_csr_rw 1.270s 44.441us 20 20 100.00
rstmgr_csr_aliasing 1.560s 56.092us 5 5 100.00
rstmgr_same_csr_outstanding 1.610s 76.414us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.260s 94.525us 5 5 100.00
rstmgr_csr_rw 1.270s 44.441us 20 20 100.00
rstmgr_csr_aliasing 1.560s 56.092us 5 5 100.00
rstmgr_same_csr_outstanding 1.610s 76.414us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 38.910s 6869.508us 5 5 100.00
rstmgr_tl_intg_err 22.580s 2731.579us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 38.910s 6869.508us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 38.910s 6869.508us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 22.580s 2731.579us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.560s 64.013us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 49 50 98.00
rstmgr_leaf_rst_cnsty 4.780s 466.373us 49 50 98.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 3.420s 291.662us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 38.910s 6869.508us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.270s 44.441us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.270s 44.441us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:*
rstmgr_leaf_rst_cnsty 106310751222771006179235135616236032471263079916555496390734245026269910588342 103
UVM_ERROR @ 154760660 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
UVM_INFO @ 154760660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---