Simulation Results: spi_host

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.82 %
  • code
  • 95.06 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 97.00 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 231.000s 37455.983us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 20.759us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 16.174us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 1288.182us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 59.856us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 105.419us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 16.174us 20 20 100.00
spi_host_csr_aliasing 2.000s 59.856us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 1.000s 16.505us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 50.731us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 93.828us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 8.000s 407.008us 50 50 100.00
spi_host_error_cmd 2.000s 55.776us 50 50 100.00
spi_host_event 663.000s 77331.949us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 7.000s 914.807us 50 50 100.00
speed 50 50 100.00
spi_host_speed 7.000s 914.807us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 7.000s 914.807us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 184.000s 6421.173us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 121.079us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 7.000s 914.807us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 7.000s 914.807us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 231.000s 37455.983us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 231.000s 37455.983us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 128.000s 9067.811us 50 50 100.00
spien 50 50 100.00
spi_host_spien 147.000s 83633.582us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 2794.000s 81023.335us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 24.000s 9536.050us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 8.000s 407.008us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 29.069us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 15.084us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 244.492us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 244.492us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 20.759us 5 5 100.00
spi_host_csr_rw 2.000s 16.174us 20 20 100.00
spi_host_csr_aliasing 2.000s 59.856us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 32.953us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 20.759us 5 5 100.00
spi_host_csr_rw 2.000s 16.174us 20 20 100.00
spi_host_csr_aliasing 2.000s 59.856us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 32.953us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 281.999us 5 5 100.00
spi_host_tl_intg_err 2.000s 539.801us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 539.801us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 340.000s 31521.619us 10 10 100.00