Simulation Results: sram_ctrl/ret

 
18/04/2026 10:17:21 DVSim: v1.17.3 sha: 75f7d2f json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.24 %
  • code
  • 83.49 %
  • assert
  • 96.43 %
  • func
  • 96.80 %
  • block
  • 94.01 %
  • line
  • 95.19 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 2.000s 82.611us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 14.289us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 24.252us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 200.862us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 17.501us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 132.227us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 24.252us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 17.501us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 7.000s 942.866us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 170.277us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 22.000s 4050.925us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 295.000s 20927.469us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 9.000s 963.673us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 21.000s 8576.171us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1904.959us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 16.000s 748.778us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 3.000s 35.017us 5 5 100.00
sram_ctrl_partial_access_b2b 377.000s 67391.708us 5 5 100.00
max_throughput 5 15 33.33
sram_ctrl_max_throughput 2.000s 22.970us 0 5 0.00
sram_ctrl_throughput_w_partial_write 2.000s 252.040us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 44.259us 0 5 0.00
regwen 5 5 100.00
sram_ctrl_regwen 13.000s 2088.484us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 37.647us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 46.000s 12239.275us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 35.994us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.000s 124.964us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.000s 124.964us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.289us 5 5 100.00
sram_ctrl_csr_rw 2.000s 24.252us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 17.501us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 21.120us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.289us 5 5 100.00
sram_ctrl_csr_rw 2.000s 24.252us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 17.501us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 21.120us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 8.000s 2706.726us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 813.808us 20 20 100.00
sram_ctrl_sec_cm 6.000s 3261.530us 5 5 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 3261.530us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 813.808us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 13.000s 2088.484us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 13.000s 2088.484us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 24.252us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 16.000s 748.778us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 16.000s 748.778us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 16.000s 748.778us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1904.959us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 136.820us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 8.000s 2706.726us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 104.961us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 82.611us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 82.611us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 16.000s 748.778us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 3261.530us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1904.959us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 3261.530us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 3261.530us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 2.000s 82.611us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 3261.530us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 37.000s 2446.717us 5 5 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 12282186188254228662385517839643051218358473155275620091126651996066408361671 102
UVM_FATAL @ 92463405 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 92463405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 31551024294053804408961325917289868334739058428041033627437393026256265568106 102
UVM_FATAL @ 89517585 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 89517585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 63235487488519769327814872183874619493746845240629291773003449834837124850060 102
UVM_FATAL @ 182731101 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 182731101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 24053279310719683844772675475752186335620616151148773691896075423883751332200 102
UVM_FATAL @ 44259397 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 44259397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 44540723399880055247506867612325045988540667149102479649291269436291604475096 102
UVM_FATAL @ 22970295 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 22970295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 108081102154666220324922709207140763174690113844493911253432656069539537057231 102
UVM_FATAL @ 23334481 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 23334481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 79966879506790319923734898112535092324765516888310959706635853300975075150509 102
UVM_FATAL @ 44602495 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 44602495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 7639097498196784679934217352442435741954802642871478475760263895194981430179 102
UVM_FATAL @ 129146983 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 129146983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 7204007987121380682740658716652135108042113974550543207301654155910975504611 102
UVM_FATAL @ 107540365 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 107540365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 57211375706537503596523398405579247591234915860600188322390144343990949310518 102
UVM_FATAL @ 107683391 ps: (sram_ctrl_base_vseq.sv:329) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-2:0], 1'b0}) <= 2; mask dist {'1 :/ 100 - partial_access_pct, [0 : '1 - 1] :/ partial_access_pct};}) Randomization failed!
UVM_INFO @ 107683391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---