Simulation Results: ac_range_check

 
19/04/2026 03:35:48 DVSim: v1.17.3 sha: 5b8f674 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.84%
V2
95.44%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 95.000s 2856.357us 19 20 95.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 110.000s 21103.576us 18 20 90.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 3.000s 46.267us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 3.000s 51.025us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 57.000s 30611.574us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 30.000s 5164.580us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 25.409us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 3.000s 51.025us 20 20 100.00
ac_range_check_csr_aliasing 30.000s 5164.580us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 39.000s 176.670us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 82.000s 17995.628us 1 1 100.00
stress_all 39 50 78.00
ac_range_check_stress_all 367.000s 11295.832us 39 50 78.00
alert_test 50 50 100.00
ac_range_check_alert_test 37.000s 42.225us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 14.783us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 411.454us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 411.454us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 46.267us 5 5 100.00
ac_range_check_csr_rw 3.000s 51.025us 20 20 100.00
ac_range_check_csr_aliasing 30.000s 5164.580us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 1581.716us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 3.000s 46.267us 5 5 100.00
ac_range_check_csr_rw 3.000s 51.025us 20 20 100.00
ac_range_check_csr_aliasing 30.000s 5164.580us 5 5 100.00
ac_range_check_same_csr_outstanding 8.000s 1581.716us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 2233.950us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 2233.950us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 2233.950us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 2233.950us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 129.000s 81617.557us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 37.000s 36.335us 5 5 100.00
ac_range_check_tl_intg_err 16.000s 306.209us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 557.000s 4044.998us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 85.000s 1231.724us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state
ac_range_check_smoke_racl 48398190221193909141085895803807478353465807696969957559511953887538628394534 4488
UVM_ERROR @ 2300937370 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2300937370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 88848428132816384908921766181405044669454574955415971651206469802429512832040 18766
UVM_ERROR @ 8303479883 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 8303479883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 91630479739316705814596081687516244124068920044375624081037485758056246728057 4926
UVM_ERROR @ 2856356582 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2856356582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 29628340247238857618687343803985380110104013058916962872065876915794947540979 4620
UVM_ERROR @ 1647528522 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1647528522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 100228873121867442647478069299557011487370984330849241899602806082606934832152 17902
UVM_ERROR @ 1887286661 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 1887286661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 89406065680789939500377566087761324277290114665314633066921133196105307228554 9584
UVM_ERROR @ 6114085563 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6114085563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 83882681578184858472043897043617100941433494935356868424308666720607648208916 4599
UVM_ERROR @ 6369695958 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 6369695958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 61340512791058043426575666378105608220230003836121391524401642063936934027534 9302
UVM_ERROR @ 2724453351 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 2724453351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 66582855870330186351874243886125613274555021768636172840405932208559866844672 21359
UVM_ERROR @ 11842807452 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 11842807452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 40528084054537805854849239955119549080367074558759761207005102572259631500056 19106
UVM_ERROR @ 30866587887 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 30866587887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 15301423775368321180279464383624099510628953905616681247387926073535825526246 4315
UVM_ERROR @ 575844401 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 575844401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 2782491132340362741113169354385888254302518593389705521668115684582442589124 4695
UVM_ERROR @ 16934557030 ps: (ac_range_check_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
UVM_INFO @ 16934557030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo.
ac_range_check_stress_all 20785463768359699310693888075659958645897655317603737675821042200335183636731 13919
UVM_ERROR @ 100509024143 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo.
UVM_INFO @ 100509024143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 94069665063949120353174406485911779721830583884965049486234278034832012641964 13272
UVM_ERROR @ 100531124557 ps: (ac_range_check_predictor.sv:163) [uvm_test_top.env.scoreboard.predict] Unable to get any item from tl_filt_d_chan_fifo.
UVM_INFO @ 100531124557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---